359 lines
11 KiB
LLVM
359 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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define i8 @ucmp.8.8(i8 %x, i8 %y) nounwind {
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; CHECK-SD-LABEL: ucmp.8.8:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: and w8, w0, #0xff
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; CHECK-SD-NEXT: cmp w8, w1, uxtb
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; CHECK-SD-NEXT: cset w8, hi
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; CHECK-SD-NEXT: csinv w0, w8, wzr, hs
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: ucmp.8.8:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: and w8, w0, #0xff
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; CHECK-GI-NEXT: and w9, w1, #0xff
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; CHECK-GI-NEXT: cmp w8, w9
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; CHECK-GI-NEXT: cset w8, hi
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; CHECK-GI-NEXT: csinv w0, w8, wzr, hs
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; CHECK-GI-NEXT: ret
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%1 = call i8 @llvm.ucmp(i8 %x, i8 %y)
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ret i8 %1
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}
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define i8 @ucmp.8.16(i16 %x, i16 %y) nounwind {
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; CHECK-SD-LABEL: ucmp.8.16:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: and w8, w0, #0xffff
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; CHECK-SD-NEXT: cmp w8, w1, uxth
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; CHECK-SD-NEXT: cset w8, hi
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; CHECK-SD-NEXT: csinv w0, w8, wzr, hs
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: ucmp.8.16:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: and w8, w0, #0xffff
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; CHECK-GI-NEXT: and w9, w1, #0xffff
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; CHECK-GI-NEXT: cmp w8, w9
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; CHECK-GI-NEXT: cset w8, hi
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; CHECK-GI-NEXT: csinv w0, w8, wzr, hs
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; CHECK-GI-NEXT: ret
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%1 = call i8 @llvm.ucmp(i16 %x, i16 %y)
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ret i8 %1
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}
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define i8 @ucmp.8.32(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: ucmp.8.32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: cset w8, hi
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; CHECK-NEXT: csinv w0, w8, wzr, hs
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; CHECK-NEXT: ret
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%1 = call i8 @llvm.ucmp(i32 %x, i32 %y)
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ret i8 %1
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}
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define i8 @ucmp.8.64(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: ucmp.8.64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, x1
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; CHECK-NEXT: cset w8, hi
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; CHECK-NEXT: csinv w0, w8, wzr, hs
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; CHECK-NEXT: ret
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%1 = call i8 @llvm.ucmp(i64 %x, i64 %y)
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ret i8 %1
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}
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define i8 @ucmp.8.128(i128 %x, i128 %y) nounwind {
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; CHECK-SD-LABEL: ucmp.8.128:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmp x2, x0
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; CHECK-SD-NEXT: sbcs xzr, x3, x1
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; CHECK-SD-NEXT: cset w8, lo
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; CHECK-SD-NEXT: cmp x0, x2
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; CHECK-SD-NEXT: sbcs xzr, x1, x3
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; CHECK-SD-NEXT: csinv w0, w8, wzr, hs
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: ucmp.8.128:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: cmp x0, x2
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; CHECK-GI-NEXT: cset w8, hi
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; CHECK-GI-NEXT: cmp x1, x3
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; CHECK-GI-NEXT: cset w9, hi
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; CHECK-GI-NEXT: csel w8, w8, w9, eq
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; CHECK-GI-NEXT: cmp x0, x2
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; CHECK-GI-NEXT: cset w9, lo
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; CHECK-GI-NEXT: cmp x1, x3
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; CHECK-GI-NEXT: cset w10, lo
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; CHECK-GI-NEXT: csel w9, w9, w10, eq
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; CHECK-GI-NEXT: tst w8, #0x1
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; CHECK-GI-NEXT: cset w8, ne
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; CHECK-GI-NEXT: tst w9, #0x1
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; CHECK-GI-NEXT: csinv w0, w8, wzr, eq
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; CHECK-GI-NEXT: ret
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%1 = call i8 @llvm.ucmp(i128 %x, i128 %y)
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ret i8 %1
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}
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define i32 @ucmp.32.32(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: ucmp.32.32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: cset w8, hi
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; CHECK-NEXT: csinv w0, w8, wzr, hs
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; CHECK-NEXT: ret
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%1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
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ret i32 %1
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}
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define i32 @ucmp.32.64(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: ucmp.32.64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, x1
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; CHECK-NEXT: cset w8, hi
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; CHECK-NEXT: csinv w0, w8, wzr, hs
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; CHECK-NEXT: ret
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%1 = call i32 @llvm.ucmp(i64 %x, i64 %y)
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ret i32 %1
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}
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define i64 @ucmp.64.64(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: ucmp.64.64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, x1
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; CHECK-NEXT: cset x8, hi
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; CHECK-NEXT: csinv x0, x8, xzr, hs
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; CHECK-NEXT: ret
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%1 = call i64 @llvm.ucmp(i64 %x, i64 %y)
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ret i64 %1
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}
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define <1 x i64> @ucmp.1.64.65(<1 x i65> %x, <1 x i65> %y) {
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; CHECK-SD-LABEL: ucmp.1.64.65:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: and x8, x1, #0x1
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; CHECK-SD-NEXT: and x9, x3, #0x1
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; CHECK-SD-NEXT: cmp x2, x0
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; CHECK-SD-NEXT: sbcs xzr, x9, x8
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; CHECK-SD-NEXT: cset x10, lo
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; CHECK-SD-NEXT: cmp x0, x2
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; CHECK-SD-NEXT: sbcs xzr, x8, x9
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; CHECK-SD-NEXT: csinv x8, x10, xzr, hs
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; CHECK-SD-NEXT: fmov d0, x8
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: ucmp.1.64.65:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: and x8, x1, #0x1
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; CHECK-GI-NEXT: and x9, x3, #0x1
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; CHECK-GI-NEXT: cmp x0, x2
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; CHECK-GI-NEXT: cset w10, hi
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; CHECK-GI-NEXT: cmp x8, x9
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; CHECK-GI-NEXT: cset w11, hi
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; CHECK-GI-NEXT: csel w10, w10, w11, eq
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; CHECK-GI-NEXT: cmp x0, x2
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; CHECK-GI-NEXT: cset w11, lo
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; CHECK-GI-NEXT: cmp x8, x9
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; CHECK-GI-NEXT: cset w8, lo
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; CHECK-GI-NEXT: csel w8, w11, w8, eq
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; CHECK-GI-NEXT: tst w10, #0x1
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; CHECK-GI-NEXT: cset x9, ne
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; CHECK-GI-NEXT: tst w8, #0x1
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; CHECK-GI-NEXT: csinv x8, x9, xzr, eq
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; CHECK-GI-NEXT: fmov d0, x8
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; CHECK-GI-NEXT: ret
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%1 = call <1 x i64> @llvm.ucmp(<1 x i65> %x, <1 x i65> %y)
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ret <1 x i64> %1
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}
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define <8 x i8> @u_v8i8(<8 x i8> %a, <8 x i8> %b) {
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; CHECK-LABEL: u_v8i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmhi v2.8b, v0.8b, v1.8b
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; CHECK-NEXT: cmhi v0.8b, v1.8b, v0.8b
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; CHECK-NEXT: sub v0.8b, v0.8b, v2.8b
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; CHECK-NEXT: ret
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entry:
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%c = call <8 x i8> @llvm.ucmp(<8 x i8> %a, <8 x i8> %b)
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ret <8 x i8> %c
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}
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define <16 x i8> @u_v16i8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: u_v16i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmhi v2.16b, v0.16b, v1.16b
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; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: sub v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: ret
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entry:
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%c = call <16 x i8> @llvm.ucmp(<16 x i8> %a, <16 x i8> %b)
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ret <16 x i8> %c
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}
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define <4 x i16> @u_v4i16(<4 x i16> %a, <4 x i16> %b) {
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; CHECK-LABEL: u_v4i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmhi v2.4h, v0.4h, v1.4h
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; CHECK-NEXT: cmhi v0.4h, v1.4h, v0.4h
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; CHECK-NEXT: sub v0.4h, v0.4h, v2.4h
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; CHECK-NEXT: ret
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entry:
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%c = call <4 x i16> @llvm.ucmp(<4 x i16> %a, <4 x i16> %b)
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ret <4 x i16> %c
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}
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define <8 x i16> @u_v8i16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: u_v8i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmhi v2.8h, v0.8h, v1.8h
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; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
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; CHECK-NEXT: sub v0.8h, v0.8h, v2.8h
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; CHECK-NEXT: ret
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entry:
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%c = call <8 x i16> @llvm.ucmp(<8 x i16> %a, <8 x i16> %b)
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ret <8 x i16> %c
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}
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define <16 x i16> @u_v16i16(<16 x i16> %a, <16 x i16> %b) {
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; CHECK-SD-LABEL: u_v16i16:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: cmhi v4.8h, v1.8h, v3.8h
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; CHECK-SD-NEXT: cmhi v5.8h, v0.8h, v2.8h
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; CHECK-SD-NEXT: cmhi v0.8h, v2.8h, v0.8h
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; CHECK-SD-NEXT: cmhi v1.8h, v3.8h, v1.8h
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; CHECK-SD-NEXT: sub v0.8h, v0.8h, v5.8h
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; CHECK-SD-NEXT: sub v1.8h, v1.8h, v4.8h
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: u_v16i16:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: cmhi v4.8h, v0.8h, v2.8h
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; CHECK-GI-NEXT: cmhi v5.8h, v1.8h, v3.8h
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; CHECK-GI-NEXT: cmhi v0.8h, v2.8h, v0.8h
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; CHECK-GI-NEXT: cmhi v1.8h, v3.8h, v1.8h
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; CHECK-GI-NEXT: sub v0.8h, v0.8h, v4.8h
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; CHECK-GI-NEXT: sub v1.8h, v1.8h, v5.8h
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; CHECK-GI-NEXT: ret
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entry:
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%c = call <16 x i16> @llvm.ucmp(<16 x i16> %a, <16 x i16> %b)
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ret <16 x i16> %c
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}
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define <2 x i32> @u_v2i32(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: u_v2i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmhi v2.2s, v0.2s, v1.2s
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; CHECK-NEXT: cmhi v0.2s, v1.2s, v0.2s
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; CHECK-NEXT: sub v0.2s, v0.2s, v2.2s
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; CHECK-NEXT: ret
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entry:
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%c = call <2 x i32> @llvm.ucmp(<2 x i32> %a, <2 x i32> %b)
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ret <2 x i32> %c
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}
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define <4 x i32> @u_v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: u_v4i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmhi v2.4s, v0.4s, v1.4s
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; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: sub v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: ret
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entry:
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%c = call <4 x i32> @llvm.ucmp(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %c
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}
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define <8 x i32> @u_v8i32(<8 x i32> %a, <8 x i32> %b) {
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; CHECK-SD-LABEL: u_v8i32:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: cmhi v4.4s, v1.4s, v3.4s
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; CHECK-SD-NEXT: cmhi v5.4s, v0.4s, v2.4s
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; CHECK-SD-NEXT: cmhi v0.4s, v2.4s, v0.4s
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; CHECK-SD-NEXT: cmhi v1.4s, v3.4s, v1.4s
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; CHECK-SD-NEXT: sub v0.4s, v0.4s, v5.4s
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; CHECK-SD-NEXT: sub v1.4s, v1.4s, v4.4s
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: u_v8i32:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: cmhi v4.4s, v0.4s, v2.4s
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; CHECK-GI-NEXT: cmhi v5.4s, v1.4s, v3.4s
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; CHECK-GI-NEXT: cmhi v0.4s, v2.4s, v0.4s
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; CHECK-GI-NEXT: cmhi v1.4s, v3.4s, v1.4s
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; CHECK-GI-NEXT: sub v0.4s, v0.4s, v4.4s
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; CHECK-GI-NEXT: sub v1.4s, v1.4s, v5.4s
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; CHECK-GI-NEXT: ret
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entry:
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%c = call <8 x i32> @llvm.ucmp(<8 x i32> %a, <8 x i32> %b)
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ret <8 x i32> %c
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}
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define <2 x i64> @u_v2i64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: u_v2i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmhi v2.2d, v0.2d, v1.2d
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; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
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; CHECK-NEXT: sub v0.2d, v0.2d, v2.2d
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; CHECK-NEXT: ret
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entry:
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%c = call <2 x i64> @llvm.ucmp(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %c
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}
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define <4 x i64> @u_v4i64(<4 x i64> %a, <4 x i64> %b) {
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; CHECK-SD-LABEL: u_v4i64:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: cmhi v4.2d, v1.2d, v3.2d
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; CHECK-SD-NEXT: cmhi v5.2d, v0.2d, v2.2d
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; CHECK-SD-NEXT: cmhi v0.2d, v2.2d, v0.2d
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; CHECK-SD-NEXT: cmhi v1.2d, v3.2d, v1.2d
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; CHECK-SD-NEXT: sub v0.2d, v0.2d, v5.2d
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; CHECK-SD-NEXT: sub v1.2d, v1.2d, v4.2d
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: u_v4i64:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: cmhi v4.2d, v0.2d, v2.2d
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; CHECK-GI-NEXT: cmhi v5.2d, v1.2d, v3.2d
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; CHECK-GI-NEXT: cmhi v0.2d, v2.2d, v0.2d
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; CHECK-GI-NEXT: cmhi v1.2d, v3.2d, v1.2d
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; CHECK-GI-NEXT: sub v0.2d, v0.2d, v4.2d
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; CHECK-GI-NEXT: sub v1.2d, v1.2d, v5.2d
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; CHECK-GI-NEXT: ret
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entry:
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%c = call <4 x i64> @llvm.ucmp(<4 x i64> %a, <4 x i64> %b)
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ret <4 x i64> %c
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}
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define <16 x i8> @signOf_neon(<8 x i16> %s0_lo, <8 x i16> %s0_hi, <8 x i16> %s1_lo, <8 x i16> %s1_hi) {
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; CHECK-SD-LABEL: signOf_neon:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: cmhi v4.8h, v1.8h, v3.8h
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; CHECK-SD-NEXT: cmhi v1.8h, v3.8h, v1.8h
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; CHECK-SD-NEXT: cmhi v3.8h, v0.8h, v2.8h
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; CHECK-SD-NEXT: cmhi v0.8h, v2.8h, v0.8h
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; CHECK-SD-NEXT: sub v1.8h, v1.8h, v4.8h
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; CHECK-SD-NEXT: sub v0.8h, v0.8h, v3.8h
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; CHECK-SD-NEXT: uzp1 v0.16b, v0.16b, v1.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: signOf_neon:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: cmhi v4.8h, v0.8h, v2.8h
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; CHECK-GI-NEXT: cmhi v5.8h, v1.8h, v3.8h
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; CHECK-GI-NEXT: cmhi v0.8h, v2.8h, v0.8h
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; CHECK-GI-NEXT: cmhi v1.8h, v3.8h, v1.8h
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; CHECK-GI-NEXT: uzp1 v0.16b, v0.16b, v1.16b
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; CHECK-GI-NEXT: uzp1 v1.16b, v4.16b, v5.16b
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; CHECK-GI-NEXT: sub v0.16b, v0.16b, v1.16b
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; CHECK-GI-NEXT: ret
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entry:
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%0 = shufflevector <8 x i16> %s0_lo, <8 x i16> %s0_hi, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%1 = shufflevector <8 x i16> %s1_lo, <8 x i16> %s1_hi, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%or.i = tail call <16 x i8> @llvm.ucmp.v16i8.v16i16(<16 x i16> %0, <16 x i16> %1)
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ret <16 x i8> %or.i
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}
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