llvm-project/llvm/test/CodeGen/AArch64/vector-global-i1.ll
Eli Friedman 696f53665d [AsmPrinter] Fix bit pattern for i1 vectors.
Vectors are defined to be tightly packed, regardless of the element
type.  The AsmPrinter didn't realize this, and was allocating extra
padding.

Fixes https://github.com/llvm/llvm-project/issues/49286
Fixes https://github.com/llvm/llvm-project/issues/53246
Fixes https://github.com/llvm/llvm-project/issues/55522

Differential Revision: https://reviews.llvm.org/D129164
2022-07-06 12:56:47 -07:00

15 lines
614 B
LLVM

; RUN: llc < %s -mtriple aarch64 | FileCheck %s
; CHECK: a:
; CHECK-NEXT: .zero 1
@a = internal constant <4 x i1> <i1 false, i1 false, i1 false, i1 false>
; CHECK: b:
; CHECK-NEXT: .byte 5
@b = internal constant <4 x i1> <i1 true, i1 false, i1 true, i1 false>
; CHECK: c:
; CHECK-NEXT: .hword 1
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .zero 1
@c = internal constant <24 x i1> <i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>