8017ca1d00
Patch was reverted due to test case (added) exposing an infinite loop in
combiner, where (shl C1, C2) create by performSHLCombine isn't
constant-folded:
Combining: t14: i64 = shl t12, Constant:i64<1>
Creating new node: t36: i64 = shl
OpaqueConstant:i64<-2401053089408754003>, Constant:i64<1>
Creating new node: t37: i64 = shl t6, Constant:i64<1>
Creating new node: t38: i64 = and t37, t36
... into: t38: i64 = and t37, t36
...
Combining: t38: i64 = and t37, t36
Creating new node: t39: i64 = and t6,
OpaqueConstant:i64<-2401053089408754003>
Creating new node: t40: i64 = shl t39, Constant:i64<1>
... into: t40: i64 = shl t39, Constant:i64<1>
and subsequently gets simplified by DAGCombiner::visitAND:
// Simplify: (and (op x...), (op y...)) -> (op (and x, y))
if (N0.getOpcode() == N1.getOpcode())
if (SDValue V = hoistLogicOpWithSameOpcodeHands(N))
return V;
before being folded by performSHLCombine once again and so on.
The combine in performSHLCombine should only be done if (shl C1, C2) can
be constant-folded, it may otherwise be unsafe and generally have a
worse end result. Thanks to Dave Sherwood for his insight on this one.
This reverts commit f719771f251d7c30eca448133fe85730f19a6bd1.
106 lines
2.4 KiB
LLVM
106 lines
2.4 KiB
LLVM
; RUN: llc -mtriple=arm64-apple-ios < %s | FileCheck %s
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define i64 @sbfiz64(i64 %v) {
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; CHECK-LABEL: sbfiz64:
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; CHECK: sbfiz x0, x0, #1, #16
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%shl = shl i64 %v, 48
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%shr = ashr i64 %shl, 47
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ret i64 %shr
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}
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define i32 @sbfiz32(i32 %v) {
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; CHECK-LABEL: sbfiz32:
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; CHECK: sbfiz w0, w0, #1, #14
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%shl = shl i32 %v, 18
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%shr = ashr i32 %shl, 17
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ret i32 %shr
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}
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define i64 @ubfiz64(i64 %v) {
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; CHECK-LABEL: ubfiz64:
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; CHECK: ubfiz x0, x0, #36, #11
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%shl = shl i64 %v, 53
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%shr = lshr i64 %shl, 17
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ret i64 %shr
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}
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define i32 @ubfiz32(i32 %v) {
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; CHECK-LABEL: ubfiz32:
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; CHECK: ubfiz w0, w0, #6, #24
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%shl = shl i32 %v, 8
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%shr = lshr i32 %shl, 2
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ret i32 %shr
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}
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define i64 @ubfiz64and(i64 %v) {
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; CHECK-LABEL: ubfiz64and:
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; CHECK: ubfiz x0, x0, #36, #11
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%shl = shl i64 %v, 36
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%and = and i64 %shl, 140668768878592
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ret i64 %and
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}
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define i32 @ubfiz32and(i32 %v) {
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; CHECK-LABEL: ubfiz32and:
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; CHECK: ubfiz w0, w0, #6, #24
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%shl = shl i32 %v, 6
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%and = and i32 %shl, 1073741760
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ret i32 %and
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}
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; Check that we don't generate a ubfiz if the lsl has more than one
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; use, since we'd just be replacing an and with a ubfiz.
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define i32 @noubfiz32(i32 %v) {
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; CHECK-LABEL: noubfiz32:
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; CHECK: lsl w[[REG1:[0-9]+]], w0, #6
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; CHECK: and w[[REG2:[0-9]+]], w[[REG1]], #0x3fffffc0
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; CHECK: add w0, w[[REG1]], w[[REG2]]
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; CHECK: ret
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%shl = shl i32 %v, 6
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%and = and i32 %shl, 1073741760
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%add = add i32 %shl, %and
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ret i32 %add
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}
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define i64 @lsl32_not_ubfiz64(i64 %v) {
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; CHECK-LABEL: lsl32_not_ubfiz64:
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; CHECK: lsl w0, w0, #6
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%shl = shl i64 %v, 6
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%and = and i64 %shl, 4294967295
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ret i64 %and
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}
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define i64 @lsl_zext_i8_i64(i8 %b) {
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; CHECK-LABEL: lsl_zext_i8_i64:
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; CHECK: ubfiz x0, x0, #1, #8
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%1 = zext i8 %b to i64
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%2 = shl i64 %1, 1
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ret i64 %2
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}
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define i64 @lsl_zext_i16_i64(i16 %b) {
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; CHECK-LABEL: lsl_zext_i16_i64:
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; CHECK: ubfiz x0, x0, #1, #16
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%1 = zext i16 %b to i64
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%2 = shl i64 %1, 1
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ret i64 %2
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}
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; Regression test for:
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; https://github.com/llvm/llvm-project/pull/118974#issuecomment-2598521878
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; that exposed infinite loop in DAGCombiner.
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define void @_f(ptr %0, ptr %1, i64 %2) {
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; CHECK-LABEL: @_f
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; CHECK-NOT: ubfiz
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store i64 -2401053089408754003, ptr %1, align 8
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%4 = and i64 %2, -2401053089408754003
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%5 = shl i64 %4, 1
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store i64 %5, ptr %0, align 1
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%6 = lshr i64 %4, 54
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%7 = shl i64 %2, 10
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%8 = and i64 %7, 131072
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%9 = or i64 %8, %6
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store i64 %9, ptr %1, align 1
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ret void
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}
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