6f7c77fe90
PR #149247 made the MD accessible by the backend so we can now leverage it in the memory model. The first use case here is detecting if a flat op can access scratch memory. Benefits both the MemoryLegalizer and InsertWaitCnt.
95 lines
3.8 KiB
LLVM
95 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GCN-SDAG %s
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL %s
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; Test that stores that may hit scratch are correctly promoted to SCOPE_SE.
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define void @test_scratch_store(ptr addrspace(5) %ptr, i32 %val) {
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; GCN-LABEL: test_scratch_store:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_wait_loadcnt_dscnt 0x0
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; GCN-NEXT: s_wait_kmcnt 0x0
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; GCN-NEXT: scratch_store_b32 v0, v1, off scope:SCOPE_SE
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; GCN-NEXT: s_set_pc_i64 s[30:31]
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store i32 %val, ptr addrspace(5) %ptr
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ret void
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}
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define void @test_unknown_flat_store(ptr %ptr, i32 %val) {
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; GCN-LABEL: test_unknown_flat_store:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_wait_loadcnt_dscnt 0x0
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; GCN-NEXT: s_wait_kmcnt 0x0
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; GCN-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
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; GCN-NEXT: s_wait_dscnt 0x0
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; GCN-NEXT: s_set_pc_i64 s[30:31]
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store i32 %val, ptr %ptr
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ret void
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}
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define void @test_flat_store_no_scratch_alloc(ptr %ptr, i32 %val) #0 {
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; GCN-LABEL: test_flat_store_no_scratch_alloc:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_wait_loadcnt_dscnt 0x0
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; GCN-NEXT: s_wait_kmcnt 0x0
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; GCN-NEXT: flat_store_b32 v[0:1], v2
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; GCN-NEXT: s_wait_dscnt 0x0
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; GCN-NEXT: s_set_pc_i64 s[30:31]
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store i32 %val, ptr %ptr
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ret void
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}
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define void @test_flat_store_noalias_addrspace(ptr %ptr, i32 %val) {
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; GCN-LABEL: test_flat_store_noalias_addrspace:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_wait_loadcnt_dscnt 0x0
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; GCN-NEXT: s_wait_kmcnt 0x0
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; GCN-NEXT: flat_store_b32 v[0:1], v2
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; GCN-NEXT: s_wait_dscnt 0x0
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; GCN-NEXT: s_set_pc_i64 s[30:31]
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store i32 %val, ptr %ptr, !noalias.addrspace !{i32 5, i32 6}
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ret void
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}
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; TODO: would be nice to handle
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define void @test_flat_store_select(ptr addrspace(1) %a, ptr addrspace(3) %b, i1 %cond, i32 %val) {
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; GCN-SDAG-LABEL: test_flat_store_select:
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; GCN-SDAG: ; %bb.0:
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; GCN-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
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; GCN-SDAG-NEXT: s_wait_kmcnt 0x0
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; GCN-SDAG-NEXT: v_cmp_ne_u32_e32 vcc_lo, -1, v2
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; GCN-SDAG-NEXT: v_and_b32_e32 v3, 1, v3
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; GCN-SDAG-NEXT: s_mov_b64 s[0:1], src_shared_base
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; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc_lo
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; GCN-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, s1, vcc_lo
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; GCN-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GCN-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
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; GCN-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v2, v0
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; GCN-SDAG-NEXT: flat_store_b32 v[0:1], v4 scope:SCOPE_SE
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; GCN-SDAG-NEXT: s_wait_dscnt 0x0
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; GCN-SDAG-NEXT: s_set_pc_i64 s[30:31]
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;
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; GCN-GISEL-LABEL: test_flat_store_select:
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; GCN-GISEL: ; %bb.0:
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; GCN-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
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; GCN-GISEL-NEXT: s_wait_kmcnt 0x0
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; GCN-GISEL-NEXT: v_cmp_ne_u32_e32 vcc_lo, -1, v2
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; GCN-GISEL-NEXT: v_and_b32_e32 v3, 1, v3
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; GCN-GISEL-NEXT: s_mov_b64 s[0:1], src_shared_base
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; GCN-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc_lo
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; GCN-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, s1, vcc_lo
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; GCN-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GCN-GISEL-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
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; GCN-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v5, v1
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; GCN-GISEL-NEXT: flat_store_b32 v[0:1], v4 scope:SCOPE_SE
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; GCN-GISEL-NEXT: s_wait_dscnt 0x0
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; GCN-GISEL-NEXT: s_set_pc_i64 s[30:31]
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%a.ascast = addrspacecast ptr addrspace(1) %a to ptr
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%b.ascast = addrspacecast ptr addrspace(3) %b to ptr
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%ptr = select i1 %cond, ptr %a.ascast, ptr %b.ascast
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store i32 %val, ptr %ptr
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ret void
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}
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attributes #0 = { "amdgpu-no-flat-scratch-init" }
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