472c9141f9
We weren't fully respecting the type of a def of an immediate vs. the type at the use point. Refactor the folding logic to track the value to fold, as well as a subregister to apply to the underlying value. This is similar to how PeepholeOpt tracks subregisters (though only for pure copy-like instructions, no constants). Fixes #139317
68 lines
3.0 KiB
LLVM
68 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefix=GFX942 %s
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; Check for correct folding of the constants produced by the
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; stepvector into the fadd. The value should not get lost when folding
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; through subregister extracts of reg_sequence.
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define amdgpu_kernel void @stepper_test_kernel_DType_I6A6AcB6A6AsA6A6A_68a5362b97a102776ef47f0e8e894a38(ptr addrspace(1) readonly captures(none) %.global, ptr addrspace(1) writeonly captures(none) %.global1, i32 %arg2) {
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; GFX942-LABEL: stepper_test_kernel_DType_I6A6AcB6A6AsA6A6A_68a5362b97a102776ef47f0e8e894a38:
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; GFX942: ; %bb.0: ; %bb
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; GFX942-NEXT: s_load_dword s6, s[4:5], 0x10
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; GFX942-NEXT: s_mov_b32 s7, 0
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; GFX942-NEXT: s_waitcnt lgkmcnt(0)
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; GFX942-NEXT: s_cmp_eq_u32 s6, 0
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; GFX942-NEXT: s_cbranch_scc1 .LBB0_3
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; GFX942-NEXT: ; %bb.1: ; %.lr.ph.preheader
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; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
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; GFX942-NEXT: s_mov_b32 s8, 0x47004600
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; GFX942-NEXT: s_mov_b32 s9, 0x45004400
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; GFX942-NEXT: s_mov_b32 s10, 0x42004000
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; GFX942-NEXT: s_mov_b64 s[4:5], 0
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; GFX942-NEXT: v_mov_b32_e32 v2, 0
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; GFX942-NEXT: v_mov_b64_e32 v[0:1], s[6:7]
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; GFX942-NEXT: .LBB0_2: ; %.lr.ph
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; GFX942-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX942-NEXT: s_waitcnt lgkmcnt(0)
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; GFX942-NEXT: global_load_dwordx4 v[4:7], v2, s[2:3]
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; GFX942-NEXT: s_add_u32 s4, s4, 8
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; GFX942-NEXT: s_addc_u32 s5, s5, 0
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; GFX942-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1]
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; GFX942-NEXT: s_waitcnt vmcnt(0)
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; GFX942-NEXT: v_pk_add_f16 v7, v7, s8
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; GFX942-NEXT: v_pk_add_f16 v6, v6, s9
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; GFX942-NEXT: v_pk_add_f16 v5, v5, s10
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; GFX942-NEXT: v_pk_add_f16 v4, v4, 1.0 op_sel:[0,1] op_sel_hi:[1,0]
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; GFX942-NEXT: global_store_dwordx4 v2, v[4:7], s[0:1]
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; GFX942-NEXT: s_add_u32 s0, s0, 16
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; GFX942-NEXT: s_addc_u32 s1, s1, 0
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; GFX942-NEXT: s_add_u32 s2, s2, 16
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; GFX942-NEXT: s_addc_u32 s3, s3, 0
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; GFX942-NEXT: s_cbranch_vccnz .LBB0_2
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; GFX942-NEXT: .LBB0_3: ; %._crit_edge
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; GFX942-NEXT: s_endpgm
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bb:
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%i = tail call <8 x i32> @llvm.stepvector.v8i32()
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%i3 = sitofp <8 x i32> %i to <8 x half>
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%i4 = zext i32 %arg2 to i64
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%.not = icmp eq i32 %arg2, 0
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br i1 %.not, label %._crit_edge, label %.lr.ph
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.lr.ph: ; preds = %.lr.ph, %bb
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%i5 = phi i64 [ %i6, %.lr.ph ], [ 0, %bb ]
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%i6 = add nuw nsw i64 %i5, 8
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%i7 = getelementptr inbounds nuw half, ptr addrspace(1) %.global1, i64 %i5
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%i8 = load <8 x half>, ptr addrspace(1) %i7, align 2
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%i9 = fadd <8 x half> %i8, %i3
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%i10 = getelementptr inbounds nuw half, ptr addrspace(1) %.global, i64 %i5
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store <8 x half> %i9, ptr addrspace(1) %i10, align 2
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%i11 = icmp samesign ult i64 %i6, %i4
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br i1 %i11, label %.lr.ph, label %._crit_edge
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._crit_edge: ; preds = %.lr.ph, %bb
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ret void
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}
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declare <8 x i32> @llvm.stepvector.v8i32() #0
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attributes #0 = { nocallback nofree nosync nounwind willreturn memory(none) }
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