56ae79a6ab
…hi values (#139605)" This relands commit b11523b494b with the fix for llvm-buildbot failures "clang-hip-vega20" and "openmp-offload-amdgpu-runtime-2". The reland prevents hoisting the phi node which fixes the issue. Original PR description: The order of if and else blocks can introduce unnecessary VGPR copies. Consider the case of an if-else block where the incoming phi from the 'Else block' only contains zero-cost instructions, and the 'Then' block modifies some value. There would be no interference when coalescing because only one value is live at any point before structurization. However, in the structurized CFG, the Then value is live at 'Else' block due to the path if→flow→else, leading to additional VGPR copies. This patch addresses the issue by: - Identifying PHI nodes with zero-cost incoming values from the Else block and hoisting those values to the nearest common dominator of the Then and Else blocks. - Updating Flow PHI nodes by replacing poison entries (on the if→flow edge) with the correct hoisted values.
181 lines
6.1 KiB
LLVM
181 lines
6.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX900 %s
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%pair = type { i32, i32 }
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define void @test_extractvalue_then_else(ptr %ptr, i1 %cond) {
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; GFX900-LABEL: test_extractvalue_then_else:
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; GFX900: ; %bb.0: ; %if
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; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX900-NEXT: flat_load_dword v3, v[0:1]
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; GFX900-NEXT: v_and_b32_e32 v2, 1, v2
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; GFX900-NEXT: v_cmp_ne_u32_e32 vcc, 1, v2
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; GFX900-NEXT: s_and_saveexec_b64 s[4:5], vcc
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; GFX900-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
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; GFX900-NEXT: s_cbranch_execz .LBB0_2
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; GFX900-NEXT: ; %bb.1: ; %else
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; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX900-NEXT: v_add_u32_e32 v3, 1, v3
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; GFX900-NEXT: .LBB0_2: ; %Flow
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; GFX900-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
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; GFX900-NEXT: s_or_b64 exec, exec, s[4:5]
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; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX900-NEXT: flat_store_dword v[0:1], v3
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; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX900-NEXT: s_setpc_b64 s[30:31]
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if:
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%load_then = load %pair, ptr %ptr
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br i1 %cond, label %then, label %else
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then:
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%a_then = extractvalue %pair %load_then, 0
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br label %merge
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else:
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%a_else = extractvalue %pair %load_then, 0
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%sum_else = add i32 %a_else, 1
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br label %merge
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merge:
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%phi = phi i32 [ %a_then, %then ], [ %sum_else, %else ]
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store i32 %phi, ptr %ptr
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ret void
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}
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define void @test_extractvalue_else_then(ptr %ptr, i1 %cond) {
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; GFX900-LABEL: test_extractvalue_else_then:
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; GFX900: ; %bb.0: ; %if
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; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX900-NEXT: flat_load_dword v3, v[0:1]
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; GFX900-NEXT: v_and_b32_e32 v2, 1, v2
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; GFX900-NEXT: v_cmp_ne_u32_e32 vcc, 1, v2
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; GFX900-NEXT: s_and_saveexec_b64 s[4:5], vcc
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; GFX900-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
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; GFX900-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
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; GFX900-NEXT: s_cbranch_execz .LBB1_2
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; GFX900-NEXT: ; %bb.1: ; %else
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; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX900-NEXT: v_add_u32_e32 v3, 1, v3
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; GFX900-NEXT: .LBB1_2: ; %merge
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; GFX900-NEXT: s_or_b64 exec, exec, s[4:5]
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; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX900-NEXT: flat_store_dword v[0:1], v3
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; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX900-NEXT: s_setpc_b64 s[30:31]
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if:
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%load_then = load %pair, ptr %ptr
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br i1 %cond, label %else, label %then
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else:
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%a_else = extractvalue %pair %load_then, 0
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%sum_else = add i32 %a_else, 1
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br label %merge
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then:
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%a_then = extractvalue %pair %load_then, 0
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br label %merge
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merge:
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%phi = phi i32 [ %a_then, %then ], [ %sum_else, %else ]
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store i32 %phi, ptr %ptr
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ret void
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}
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define amdgpu_kernel void @test_loop_with_if( ptr %ptr, i1 %cond) #0 {
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; GFX900-LABEL: test_loop_with_if:
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; GFX900: ; %bb.0: ; %entry
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; GFX900-NEXT: s_load_dword s2, s[4:5], 0x2c
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; GFX900-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GFX900-NEXT: v_mov_b32_e32 v5, 0
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; GFX900-NEXT: s_mov_b64 s[4:5], 0
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; GFX900-NEXT: s_movk_i32 s10, 0xfe
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; GFX900-NEXT: s_waitcnt lgkmcnt(0)
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; GFX900-NEXT: s_bitcmp1_b32 s2, 0
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; GFX900-NEXT: s_cselect_b64 s[2:3], -1, 0
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; GFX900-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[2:3]
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; GFX900-NEXT: v_mov_b32_e32 v2, s1
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; GFX900-NEXT: s_xor_b64 s[2:3], s[2:3], -1
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; GFX900-NEXT: v_mov_b32_e32 v1, s0
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; GFX900-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v3
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; GFX900-NEXT: s_branch .LBB2_2
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; GFX900-NEXT: .LBB2_1: ; %latch
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; GFX900-NEXT: ; in Loop: Header=BB2_2 Depth=1
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; GFX900-NEXT: s_or_b64 exec, exec, s[8:9]
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; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX900-NEXT: v_add_u32_e32 v5, 20, v3
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; GFX900-NEXT: v_cmp_lt_i32_e32 vcc, s10, v5
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; GFX900-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
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; GFX900-NEXT: flat_store_dword v[1:2], v3
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; GFX900-NEXT: s_andn2_b64 exec, exec, s[4:5]
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; GFX900-NEXT: s_cbranch_execz .LBB2_8
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; GFX900-NEXT: .LBB2_2: ; %loop
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; GFX900-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX900-NEXT: flat_load_dwordx2 v[3:4], v[1:2]
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; GFX900-NEXT: s_and_b64 vcc, exec, s[0:1]
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; GFX900-NEXT: s_mov_b64 s[8:9], s[2:3]
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; GFX900-NEXT: s_mov_b64 s[6:7], 0
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; GFX900-NEXT: s_cbranch_vccnz .LBB2_4
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; GFX900-NEXT: ; %bb.3: ; %if
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; GFX900-NEXT: ; in Loop: Header=BB2_2 Depth=1
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; GFX900-NEXT: v_cmp_gt_i32_e32 vcc, 11, v5
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; GFX900-NEXT: s_andn2_b64 s[8:9], s[2:3], exec
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; GFX900-NEXT: s_and_b64 s[12:13], vcc, exec
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; GFX900-NEXT: s_mov_b64 s[6:7], -1
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; GFX900-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13]
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; GFX900-NEXT: .LBB2_4: ; %Flow
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; GFX900-NEXT: ; in Loop: Header=BB2_2 Depth=1
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; GFX900-NEXT: s_and_saveexec_b64 s[12:13], s[8:9]
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; GFX900-NEXT: s_xor_b64 s[8:9], exec, s[12:13]
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; GFX900-NEXT: s_cbranch_execz .LBB2_6
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; GFX900-NEXT: ; %bb.5: ; %else
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; GFX900-NEXT: ; in Loop: Header=BB2_2 Depth=1
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; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX900-NEXT: v_add_u32_e32 v3, v3, v4
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; GFX900-NEXT: s_andn2_b64 s[6:7], s[6:7], exec
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; GFX900-NEXT: .LBB2_6: ; %Flow1
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; GFX900-NEXT: ; in Loop: Header=BB2_2 Depth=1
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; GFX900-NEXT: s_or_b64 exec, exec, s[8:9]
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; GFX900-NEXT: s_and_saveexec_b64 s[8:9], s[6:7]
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; GFX900-NEXT: s_cbranch_execz .LBB2_1
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; GFX900-NEXT: ; %bb.7: ; %then
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; GFX900-NEXT: ; in Loop: Header=BB2_2 Depth=1
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; GFX900-NEXT: flat_store_dword v[1:2], v0
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; GFX900-NEXT: s_branch .LBB2_1
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; GFX900-NEXT: .LBB2_8: ; %end
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; GFX900-NEXT: s_endpgm
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entry:
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%a = tail call i32 @llvm.amdgcn.workitem.id.x()
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br label %loop
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loop:
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%entry_phi = phi i32 [ 0, %entry ], [ %a15, %latch ]
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%load = load %pair, ptr %ptr
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br i1 %cond, label %if, label %else
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if:
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%cmp = icmp sgt i32 %entry_phi, 10
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br i1 %cmp, label %then, label %else
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then:
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%a_then = extractvalue %pair %load, 0
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store i32 %a, ptr %ptr, align 4
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br label %latch
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else:
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%a2 = extractvalue %pair %load, 1
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%y = extractvalue %pair %load, 0
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%a_else = add i32 %y, %a2
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br label %latch
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latch:
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%a_test = phi i32 [ %a_then, %then ], [ %a_else, %else ]
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store i32 %a_test, ptr %ptr
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%a15 = add nsw i32 %a_test, 20
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%a16 = icmp slt i32 %a15, 255
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br i1 %a16, label %loop, label %end
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end:
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ret void
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}
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