llvm-project/llvm/test/CodeGen/AMDGPU/subvector-test.mir
Fangrui Song 9e9907f1cf
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
Similar to 806761a7629df268c8aed49657aeccffa6bca449.

For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.

Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.

This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:

```
  LLVM :: CodeGen/AMDGPU/fabs.f64.ll
  LLVM :: CodeGen/AMDGPU/fabs.ll
  LLVM :: CodeGen/AMDGPU/floor.ll
  LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
  LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
  LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
  LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
2024-01-16 21:54:58 -08:00

38 lines
1.3 KiB
YAML

# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -start-before=greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -start-before=greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
...
# GCN-LABEL: {{^}}"subvector-basic-bb"
# GCN: s_subvector_loop_begin [[RS:s[0-9]]], .LBB0_2
# GCN: s_subvector_loop_end [[RS]], .LBB0_1
name: subvector-basic-bb
tracksRegLiveness: true
machineFunctionInfo:
scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
frameOffsetReg: $sgpr5
stackPtrOffsetReg: $sgpr32
body: |
bb.0:
liveins: $sgpr0_sgpr1
successors: %bb.1, %bb.2
%1:sgpr_64 = COPY $sgpr0_sgpr1
%4:sgpr_128 = S_LOAD_DWORDX4_IMM %1, 36, 0
%11:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4.sub2_sub3, 0, 0
undef %15.sub0:vreg_64 = COPY %4.sub0
%15.sub1:vreg_64 = COPY %4.sub1
%16:vgpr_32 = COPY %1.sub0
S_SUBVECTOR_LOOP_BEGIN %bb.2, undef %19:sreg_32, implicit-def $exec, implicit $exec, implicit-def %19
bb.1:
successors: %bb.1, %bb.2
%14:sreg_32_xm0 = S_ADD_I32 %11.sub0, %11.sub1, implicit-def dead $scc
%16:vgpr_32 = COPY %14
S_SUBVECTOR_LOOP_END %bb.1, %19:sreg_32, implicit-def $exec, implicit $exec, implicit-def %19
bb.2:
GLOBAL_STORE_DWORD %15, %16, 0, 0, implicit $exec
S_ENDPGM 0
...