fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
133 lines
4.9 KiB
LLVM
133 lines
4.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn < %s | FileCheck %s
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; RUN: llc -mtriple=amdgcn -early-live-intervals < %s | FileCheck %s
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; We may have subregister live ranges that are undefined on some paths. The
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; verifier should not complain about this.
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define amdgpu_kernel void @func() #0 {
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; CHECK-LABEL: func:
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; CHECK: ; %bb.0: ; %B0
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; CHECK-NEXT: s_cmp_lg_u32 s8, 0
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; CHECK-NEXT: s_mov_b32 s0, 0
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; CHECK-NEXT: s_cbranch_scc1 .LBB0_2
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; CHECK-NEXT: ; %bb.1: ; %B30.1
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; CHECK-NEXT: s_mov_b32 s0, 0x7fc00000
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; CHECK-NEXT: .LBB0_2: ; %B30.2
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; CHECK-NEXT: v_mov_b32_e32 v0, s0
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; CHECK-NEXT: s_mov_b32 m0, -1
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; CHECK-NEXT: ds_write_b32 v0, v0
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; CHECK-NEXT: s_endpgm
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B0:
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%id = call i32 @llvm.amdgcn.workgroup.id.x()
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%cmp = icmp eq i32 %id, 0
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br i1 %cmp, label %B1, label %B2
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B1:
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br label %B2
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B2:
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%v0 = phi <4 x float> [ zeroinitializer, %B1 ], [ <float 0.0, float 0.0, float 0.0, float poison>, %B0 ]
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br i1 %cmp, label %B30.1, label %B30.2
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B30.1:
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%sub = fsub <4 x float> %v0, splat (float 0x7FF8000000000000)
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br label %B30.2
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B30.2:
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%v3 = phi <4 x float> [ %sub, %B30.1 ], [ %v0, %B2 ]
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%ve0 = extractelement <4 x float> %v3, i32 0
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store float %ve0, ptr addrspace(3) poison, align 4
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ret void
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}
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; FIXME: Extra undef subregister copy should be removed before
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; overwritten with defined copy
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define amdgpu_ps float @valley_partially_undef_copy() #0 {
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; CHECK-LABEL: valley_partially_undef_copy:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_mov_b32 s3, 0xf000
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; CHECK-NEXT: s_mov_b32 s2, -1
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; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v2, 0x7fc00000
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; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
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; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], 0
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
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; CHECK-NEXT: s_waitcnt expcnt(1)
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; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
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; CHECK-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v1
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; CHECK-NEXT: .LBB1_1: ; %bb9
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: s_and_b64 vcc, exec, s[0:1]
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; CHECK-NEXT: s_cbranch_vccnz .LBB1_1
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; CHECK-NEXT: ; %bb.2: ; %bb11
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; CHECK-NEXT: s_mov_b32 s3, 0xf000
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; CHECK-NEXT: s_mov_b32 s2, -1
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; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0)
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; CHECK-NEXT: ; return to shader part epilog
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bb:
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%tmp = load volatile i32, ptr addrspace(1) poison, align 4
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%tmp1 = load volatile i32, ptr addrspace(1) poison, align 4
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%tmp2 = insertelement <4 x i32> poison, i32 %tmp1, i32 0
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%tmp3 = bitcast i32 %tmp1 to float
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%tmp4 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %tmp3, float %tmp3, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
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%tmp5 = extractelement <4 x float> %tmp4, i32 0
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%tmp6 = fmul float %tmp5, 0x7FF8000000000000
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%tmp7 = fadd float %tmp6, %tmp6
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%tmp8 = insertelement <4 x i32> %tmp2, i32 %tmp, i32 1
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store <4 x i32> %tmp8, ptr addrspace(1) poison, align 16
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store float %tmp7, ptr addrspace(1) poison, align 4
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br label %bb9
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bb9: ; preds = %bb9, %bb
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%tmp10 = icmp eq i32 %tmp, 0
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br i1 %tmp10, label %bb9, label %bb11
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bb11: ; preds = %bb9
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store <4 x i32> %tmp2, ptr addrspace(1) poison, align 16
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ret float poison
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}
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; FIXME: Should be able to remove the undef copies
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define amdgpu_kernel void @partially_undef_copy() #0 {
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; CHECK-LABEL: partially_undef_copy:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: v_mov_b32_e32 v5, 5
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: v_mov_b32_e32 v6, 6
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_mov_b32_e32 v0, v5
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; CHECK-NEXT: v_mov_b32_e32 v1, v6
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; CHECK-NEXT: v_mov_b32_e32 v2, v7
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; CHECK-NEXT: v_mov_b32_e32 v3, v8
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; CHECK-NEXT: s_mov_b32 s3, 0xf000
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; CHECK-NEXT: s_mov_b32 s2, -1
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; CHECK-NEXT: v_mov_b32_e32 v0, v6
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; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: v_nop
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_endpgm
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%tmp0 = call i32 asm sideeffect "v_mov_b32_e32 v5, 5", "={v5}"()
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%tmp1 = call i32 asm sideeffect "v_mov_b32_e32 v6, 6", "={v6}"()
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%partially.undef.0 = insertelement <4 x i32> poison, i32 %tmp0, i32 0
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%partially.undef.1 = insertelement <4 x i32> %partially.undef.0, i32 %tmp1, i32 0
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store volatile <4 x i32> %partially.undef.1, ptr addrspace(1) poison, align 16
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tail call void asm sideeffect "v_nop", "v={v[5:8]}"(<4 x i32> %partially.undef.0)
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ret void
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}
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declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readonly }
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