9ef1d37ffb
Similar to 806761a7629df268c8aed49657aeccffa6bca449 -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize avr-apple-darwin as ELF instead of rejecting it outrightly.
145 lines
3.2 KiB
LLVM
145 lines
3.2 KiB
LLVM
; RUN: llc -mtriple=avr -filetype=asm -O1 < %s | FileCheck %s
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define void @check60(ptr %1) {
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; CHECK-LABEL: check60:
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; CHECK-NEXT: %bb.0
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; CHECK-NEXT: mov r30, r24
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; CHECK-NEXT: mov r31, r25
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; CHECK-NEXT: ldd r24, Z+60
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; CHECK-NEXT: ldd r25, Z+61
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; CHECK-NEXT: ldd r18, Z+62
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; CHECK-NEXT: ldd r19, Z+63
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; CHECK-NEXT: sts 3, r19
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; CHECK-NEXT: sts 2, r18
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; CHECK-NEXT: sts 1, r25
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; CHECK-NEXT: sts 0, r24
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; CHECK-NEXT: ret
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bb0:
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%2 = getelementptr i8, ptr %1, i16 60
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%3 = load i32, ptr %2, align 1
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store i32 %3, ptr null, align 1
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ret void
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}
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define void @check61(ptr %1) {
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; CHECK-LABEL: check61:
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; CHECK-NEXT: %bb.0
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; CHECK-NEXT: mov r30, r24
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; CHECK-NEXT: mov r31, r25
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; CHECK-NEXT: ldd r18, Z+61
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; CHECK-NEXT: ldd r19, Z+62
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; CHECK-NEXT: adiw r24, 63
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; CHECK-NEXT: mov r30, r24
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; CHECK-NEXT: mov r31, r25
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; CHECK-NEXT: ld r24, Z
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; CHECK-NEXT: ldd r25, Z+1
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; CHECK-NEXT: sts 3, r25
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; CHECK-NEXT: sts 2, r24
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; CHECK-NEXT: sts 1, r19
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; CHECK-NEXT: sts 0, r18
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; CHECK-NEXT: ret
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bb0:
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%2 = getelementptr i8, ptr %1, i16 61
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%3 = load i32, ptr %2, align 1
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store i32 %3, ptr null, align 1
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ret void
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}
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define void @check62(ptr %1) {
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; CHECK-LABEL: check62:
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; CHECK-NEXT: %bb.0
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; CHECK-NEXT: mov r30, r24
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; CHECK-NEXT: mov r31, r25
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; CHECK-NEXT: ldd r18, Z+62
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; CHECK-NEXT: ldd r19, Z+63
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; CHECK-NEXT: adiw r24, 62
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; CHECK-NEXT: mov r30, r24
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; CHECK-NEXT: mov r31, r25
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; CHECK-NEXT: ldd r24, Z+2
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; CHECK-NEXT: ldd r25, Z+3
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; CHECK-NEXT: sts 3, r25
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; CHECK-NEXT: sts 2, r24
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; CHECK-NEXT: sts 1, r19
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; CHECK-NEXT: sts 0, r18
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; CHECK-NEXT: ret
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bb0:
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%2 = getelementptr i8, ptr %1, i16 62
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%3 = load i32, ptr %2, align 1
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store i32 %3, ptr null, align 1
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ret void
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}
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define void @check63(ptr %1) {
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; CHECK-LABEL: check63:
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; CHECK-NEXT: %bb.0
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; CHECK-NEXT: adiw r24, 63
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; CHECK-NEXT: mov r30, r24
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; CHECK-NEXT: mov r31, r25
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; CHECK-NEXT: ld r24, Z
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; CHECK-NEXT: ldd r25, Z+1
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; CHECK-NEXT: ldd r18, Z+2
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; CHECK-NEXT: ldd r19, Z+3
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; CHECK-NEXT: sts 3, r19
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; CHECK-NEXT: sts 2, r18
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; CHECK-NEXT: sts 1, r25
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; CHECK-NEXT: sts 0, r24
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; CHECK-NEXT: ret
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bb0:
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%2 = getelementptr i8, ptr %1, i16 63
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%3 = load i32, ptr %2, align 1
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store i32 %3, ptr null, align 1
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ret void
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}
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define void @check64(ptr %1) {
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; CHECK-LABEL: check64:
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; CHECK-NEXT: %bb.0
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; CHECK-NEXT: subi r24, 192
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; CHECK-NEXT: sbci r25, 255
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; CHECK-NEXT: mov r30, r24
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; CHECK-NEXT: mov r31, r25
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; CHECK-NEXT: ld r24, Z
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; CHECK-NEXT: ldd r25, Z+1
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; CHECK-NEXT: ldd r18, Z+2
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; CHECK-NEXT: ldd r19, Z+3
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; CHECK-NEXT: sts 3, r19
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; CHECK-NEXT: sts 2, r18
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; CHECK-NEXT: sts 1, r25
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; CHECK-NEXT: sts 0, r24
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; CHECK-NEXT: ret
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bb0:
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%2 = getelementptr i8, ptr %1, i16 64
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%3 = load i32, ptr %2, align 1
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store i32 %3, ptr null, align 1
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ret void
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}
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define void @check65(ptr %1) {
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; CHECK-LABEL: check65:
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; CHECK-NEXT: %bb.0
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; CHECK-NEXT: subi r24, 191
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; CHECK-NEXT: sbci r25, 255
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; CHECK-NEXT: mov r30, r24
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; CHECK-NEXT: mov r31, r25
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; CHECK-NEXT: ld r24, Z
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; CHECK-NEXT: ldd r25, Z+1
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; CHECK-NEXT: ldd r18, Z+2
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; CHECK-NEXT: ldd r19, Z+3
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; CHECK-NEXT: sts 3, r19
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; CHECK-NEXT: sts 2, r18
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; CHECK-NEXT: sts 1, r25
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; CHECK-NEXT: sts 0, r24
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; CHECK-NEXT: ret
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bb0:
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%2 = getelementptr i8, ptr %1, i16 65
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%3 = load i32, ptr %2, align 1
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store i32 %3, ptr null, align 1
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ret void
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}
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