4ad517e6b0
CSKY arch has multiple FPU instruction versions such as FPU, FPUv2 and FPUv3 to implement floating operations. For now, we just only support FPUv2 and FPUv3. It includes the encoding, asm parsing of instructions and codegen of DAG nodes.
335 lines
8.3 KiB
LLVM
335 lines
8.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf | FileCheck %s --check-prefix=CHECK-SF
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; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf | FileCheck %s --check-prefix=CHECK-SF2
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; float --> i32
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define i32 @fptosiR_float_1(float %x) {
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;
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; CHECK-SF-LABEL: fptosiR_float_1:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: fstosi.rz vr0, vr0
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; CHECK-SF-NEXT: fmfvrl a0, vr0
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: fptosiR_float_1:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: fftoi.f32.s32.rz vr0, vr0
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; CHECK-SF2-NEXT: fmfvr.32.1 a0, vr0
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; CHECK-SF2-NEXT: rts16
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entry:
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%fptosi = fptosi float %x to i32
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ret i32 %fptosi
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}
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; float --> i16
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define i16 @fptosiR_float_2(float %x) {
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;
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; CHECK-SF-LABEL: fptosiR_float_2:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: fstosi.rz vr0, vr0
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; CHECK-SF-NEXT: fmfvrl a0, vr0
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: fptosiR_float_2:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: fftoi.f32.s32.rz vr0, vr0
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; CHECK-SF2-NEXT: fmfvr.32.1 a0, vr0
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; CHECK-SF2-NEXT: rts16
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entry:
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%fptosi = fptosi float %x to i16
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ret i16 %fptosi
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}
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; float --> i8
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define i8 @fptosiR_float_3(float %x) {
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;
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; CHECK-SF-LABEL: fptosiR_float_3:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: fstosi.rz vr0, vr0
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; CHECK-SF-NEXT: fmfvrl a0, vr0
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: fptosiR_float_3:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: fftoi.f32.s32.rz vr0, vr0
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; CHECK-SF2-NEXT: fmfvr.32.1 a0, vr0
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; CHECK-SF2-NEXT: rts16
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entry:
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%fptosi = fptosi float %x to i8
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ret i8 %fptosi
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}
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; float --> i1
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define i1 @fptosiR_float_4(float %x) {
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;
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; CHECK-SF-LABEL: fptosiR_float_4:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: fstosi.rz vr0, vr0
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; CHECK-SF-NEXT: fmfvrl a0, vr0
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: fptosiR_float_4:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: fftoi.f32.s32.rz vr0, vr0
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; CHECK-SF2-NEXT: fmfvr.32.1 a0, vr0
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; CHECK-SF2-NEXT: rts16
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entry:
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%fptosi = fptosi float %x to i1
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ret i1 %fptosi
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}
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; float --> i32
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define i32 @fptouiR_float_1(float %x) {
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;
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; CHECK-SF-LABEL: fptouiR_float_1:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: fstoui.rz vr0, vr0
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; CHECK-SF-NEXT: fmfvrl a0, vr0
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: fptouiR_float_1:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: fftoi.f32.u32.rz vr0, vr0
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; CHECK-SF2-NEXT: fmfvr.32.1 a0, vr0
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; CHECK-SF2-NEXT: rts16
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entry:
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%fptoui = fptoui float %x to i32
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ret i32 %fptoui
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}
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; float --> i16
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define i16 @fptouiR_float_2(float %x) {
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;
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; CHECK-SF-LABEL: fptouiR_float_2:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: fstoui.rz vr0, vr0
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; CHECK-SF-NEXT: fmfvrl a0, vr0
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: fptouiR_float_2:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: fftoi.f32.u32.rz vr0, vr0
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; CHECK-SF2-NEXT: fmfvr.32.1 a0, vr0
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; CHECK-SF2-NEXT: rts16
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entry:
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%fptoui = fptoui float %x to i16
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ret i16 %fptoui
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}
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; float --> i8
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define i8 @fptouiR_float_3(float %x) {
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;
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; CHECK-SF-LABEL: fptouiR_float_3:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: fstoui.rz vr0, vr0
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; CHECK-SF-NEXT: fmfvrl a0, vr0
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: fptouiR_float_3:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: fftoi.f32.u32.rz vr0, vr0
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; CHECK-SF2-NEXT: fmfvr.32.1 a0, vr0
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; CHECK-SF2-NEXT: rts16
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entry:
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%fptoui = fptoui float %x to i8
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ret i8 %fptoui
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}
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; float --> i1
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define i1 @fptouiR_float_4(float %x) {
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;
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; CHECK-SF-LABEL: fptouiR_float_4:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: fstoui.rz vr0, vr0
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; CHECK-SF-NEXT: fmfvrl a0, vr0
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: fptouiR_float_4:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: fftoi.f32.u32.rz vr0, vr0
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; CHECK-SF2-NEXT: fmfvr.32.1 a0, vr0
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; CHECK-SF2-NEXT: rts16
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entry:
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%fptoui = fptoui float %x to i1
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ret i1 %fptoui
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}
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; i32/i16/i8/i1 --> float
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define float @sitofpR_float_0(i32 %x) {
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;
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; CHECK-SF-LABEL: sitofpR_float_0:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: fmtvrl vr0, a0
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; CHECK-SF-NEXT: fsitos vr0, vr0
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: sitofpR_float_0:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: fmtvr.32.1 vr0, a0
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; CHECK-SF2-NEXT: fitof.s32.f32 vr0, vr0
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; CHECK-SF2-NEXT: rts16
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entry:
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%sitofp = sitofp i32 %x to float
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ret float %sitofp
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}
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define float @sitofpR_float_1(i16 %x) {
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;
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; CHECK-SF-LABEL: sitofpR_float_1:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: sexth16 a0, a0
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; CHECK-SF-NEXT: fmtvrl vr0, a0
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; CHECK-SF-NEXT: fsitos vr0, vr0
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: sitofpR_float_1:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: sexth16 a0, a0
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; CHECK-SF2-NEXT: fmtvr.32.1 vr0, a0
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; CHECK-SF2-NEXT: fitof.s32.f32 vr0, vr0
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; CHECK-SF2-NEXT: rts16
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entry:
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%sitofp = sitofp i16 %x to float
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ret float %sitofp
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}
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define float @sitofpR_float_2(i8 %x) {
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;
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; CHECK-SF-LABEL: sitofpR_float_2:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: sextb16 a0, a0
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; CHECK-SF-NEXT: fmtvrl vr0, a0
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; CHECK-SF-NEXT: fsitos vr0, vr0
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: sitofpR_float_2:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: sextb16 a0, a0
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; CHECK-SF2-NEXT: fmtvr.32.1 vr0, a0
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; CHECK-SF2-NEXT: fitof.s32.f32 vr0, vr0
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; CHECK-SF2-NEXT: rts16
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entry:
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%sitofp = sitofp i8 %x to float
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ret float %sitofp
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}
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define float @sitofpR_float_3(i1 %x) {
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;
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; CHECK-SF-LABEL: sitofpR_float_3:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: sext32 a0, a0, 0, 0
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; CHECK-SF-NEXT: fmtvrl vr0, a0
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; CHECK-SF-NEXT: fsitos vr0, vr0
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: sitofpR_float_3:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: sext32 a0, a0, 0, 0
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; CHECK-SF2-NEXT: fmtvr.32.1 vr0, a0
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; CHECK-SF2-NEXT: fitof.s32.f32 vr0, vr0
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; CHECK-SF2-NEXT: rts16
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entry:
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%sitofp = sitofp i1 %x to float
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ret float %sitofp
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}
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; i32/i16/i8/i1 --> float
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define float @uitofpR_float_0(i32 %x) {
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;
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; CHECK-SF-LABEL: uitofpR_float_0:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: fmtvrl vr0, a0
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; CHECK-SF-NEXT: fuitos vr0, vr0
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: uitofpR_float_0:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: fmtvr.32.1 vr0, a0
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; CHECK-SF2-NEXT: fitof.u32.f32 vr0, vr0
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; CHECK-SF2-NEXT: rts16
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entry:
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%uitofp = uitofp i32 %x to float
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ret float %uitofp
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}
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define float @uitofpR_float_1(i16 %x) {
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;
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; CHECK-SF-LABEL: uitofpR_float_1:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: zexth16 a0, a0
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; CHECK-SF-NEXT: fmtvrl vr0, a0
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; CHECK-SF-NEXT: fuitos vr0, vr0
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: uitofpR_float_1:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: zexth16 a0, a0
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; CHECK-SF2-NEXT: fmtvr.32.1 vr0, a0
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; CHECK-SF2-NEXT: fitof.u32.f32 vr0, vr0
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; CHECK-SF2-NEXT: rts16
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entry:
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%uitofp = uitofp i16 %x to float
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ret float %uitofp
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}
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define float @uitofpR_float_2(i8 %x) {
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;
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; CHECK-SF-LABEL: uitofpR_float_2:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: zextb16 a0, a0
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; CHECK-SF-NEXT: fmtvrl vr0, a0
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; CHECK-SF-NEXT: fuitos vr0, vr0
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: uitofpR_float_2:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: zextb16 a0, a0
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; CHECK-SF2-NEXT: fmtvr.32.1 vr0, a0
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; CHECK-SF2-NEXT: fitof.u32.f32 vr0, vr0
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; CHECK-SF2-NEXT: rts16
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entry:
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%uitofp = uitofp i8 %x to float
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ret float %uitofp
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}
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define float @uitofpR_float_3(i1 %x) {
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;
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; CHECK-SF-LABEL: uitofpR_float_3:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: andi32 a0, a0, 1
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; CHECK-SF-NEXT: fmtvrl vr0, a0
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; CHECK-SF-NEXT: fuitos vr0, vr0
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: uitofpR_float_3:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: andi32 a0, a0, 1
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; CHECK-SF2-NEXT: fmtvr.32.1 vr0, a0
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; CHECK-SF2-NEXT: fitof.u32.f32 vr0, vr0
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; CHECK-SF2-NEXT: rts16
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entry:
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%uitofp = uitofp i1 %x to float
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ret float %uitofp
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}
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