2208c97c1b
Similar to 806761a7629df268c8aed49657aeccffa6bca449 -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly.
85 lines
3.1 KiB
LLVM
85 lines
3.1 KiB
LLVM
; RUN: llc -mtriple=hexagon < %s | FileCheck %s
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; RUN: llc -mtriple=hexagon -verify-machineinstrs=true < %s | FileCheck %s
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; Testing bitreverse load intrinsics:
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; Q6_bitrev_load_update_D(inputLR, pDelay, nConvLength);
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; Q6_bitrev_load_update_W(inputLR, pDelay, nConvLength);
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; Q6_bitrev_load_update_H(inputLR, pDelay, nConvLength);
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; Q6_bitrev_load_update_UH(inputLR, pDelay, nConvLength);
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; Q6_bitrev_load_update_UB(inputLR, pDelay, nConvLength);
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; Q6_bitrev_load_update_B(inputLR, pDelay, nConvLength);
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; producing these instructions:
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; r3:2 = memd(r0++m0:brev)
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; r1 = memw(r0++m0:brev)
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; r1 = memh(r0++m0:brev)
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; r1 = memuh(r0++m0:brev)
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; r1 = memub(r0++m0:brev)
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; r1 = memb(r0++m0:brev)
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon-unknown--elf"
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; CHECK: @call_brev_ldd
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define ptr @call_brev_ldd(ptr %ptr, i64 %dst, i32 %mod) local_unnamed_addr #0 {
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entry:
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; CHECK: = memd(r{{[0-9]*}}++m{{[0-1]}}:brev)
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%0 = tail call { i64, ptr } @llvm.hexagon.L2.loadrd.pbr(ptr %ptr, i32 %mod)
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%1 = extractvalue { i64, ptr } %0, 1
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ret ptr %1
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}
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; CHECK: @call_brev_ldw
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define ptr @call_brev_ldw(ptr %ptr, i32 %dst, i32 %mod) local_unnamed_addr #0 {
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entry:
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; CHECK: = memw(r{{[0-9]*}}++m{{[0-1]}}:brev)
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%0 = tail call { i32, ptr } @llvm.hexagon.L2.loadri.pbr(ptr %ptr, i32 %mod)
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%1 = extractvalue { i32, ptr } %0, 1
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ret ptr %1
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}
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; CHECK: @call_brev_ldh
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define ptr @call_brev_ldh(ptr %ptr, i16 signext %dst, i32 %mod) local_unnamed_addr #0 {
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entry:
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; CHECK: = memh(r{{[0-9]*}}++m{{[0-1]}}:brev)
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%0 = tail call { i32, ptr } @llvm.hexagon.L2.loadrh.pbr(ptr %ptr, i32 %mod)
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%1 = extractvalue { i32, ptr } %0, 1
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ret ptr %1
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}
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; CHECK: @call_brev_lduh
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define ptr @call_brev_lduh(ptr %ptr, i16 zeroext %dst, i32 %mod) local_unnamed_addr #0 {
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entry:
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; CHECK: = memuh(r{{[0-9]*}}++m{{[0-1]}}:brev)
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%0 = tail call { i32, ptr } @llvm.hexagon.L2.loadruh.pbr(ptr %ptr, i32 %mod)
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%1 = extractvalue { i32, ptr } %0, 1
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ret ptr %1
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}
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; CHECK: @call_brev_ldb
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define ptr @call_brev_ldb(ptr %ptr, i8 signext %dst, i32 %mod) local_unnamed_addr #0 {
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entry:
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; CHECK: = memb(r{{[0-9]*}}++m{{[0-1]}}:brev)
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%0 = tail call { i32, ptr } @llvm.hexagon.L2.loadrb.pbr(ptr %ptr, i32 %mod)
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%1 = extractvalue { i32, ptr } %0, 1
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ret ptr %1
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}
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; Function Attrs: nounwind readonly
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; CHECK: @call_brev_ldub
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define ptr @call_brev_ldub(ptr %ptr, i8 zeroext %dst, i32 %mod) local_unnamed_addr #0 {
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entry:
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; CHECK: = memub(r{{[0-9]*}}++m{{[0-1]}}:brev)
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%0 = tail call { i32, ptr } @llvm.hexagon.L2.loadrub.pbr(ptr %ptr, i32 %mod)
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%1 = extractvalue { i32, ptr } %0, 1
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ret ptr %1
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}
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declare { i64, ptr } @llvm.hexagon.L2.loadrd.pbr(ptr, i32) #1
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declare { i32, ptr } @llvm.hexagon.L2.loadri.pbr(ptr, i32) #1
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declare { i32, ptr } @llvm.hexagon.L2.loadrh.pbr(ptr, i32) #1
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declare { i32, ptr } @llvm.hexagon.L2.loadruh.pbr(ptr, i32) #1
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declare { i32, ptr } @llvm.hexagon.L2.loadrb.pbr(ptr, i32) #1
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declare { i32, ptr } @llvm.hexagon.L2.loadrub.pbr(ptr, i32) #1
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attributes #0 = { nounwind readonly "target-cpu"="hexagonv60" }
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attributes #1 = { nounwind readonly }
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