37559c8401
This commit updates the Hexagon backend to handle vxi1 call operands. It ensures compatibility for vector types of sizes 4, 8, 16, 32, 64, and 128 x i1 when HVX is enabled. ~Fixes #59009 and #118879~
40 lines
1.2 KiB
LLVM
40 lines
1.2 KiB
LLVM
;RUN: llc -mtriple=hexagon < %s -o - | FileCheck %s --check-prefix=CHECK
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;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length64b < %s -o - | FileCheck %s --check-prefix=CHECK
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;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s -o - | FileCheck %s --check-prefix=CHECK
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; CHECK-LABEL: compare_vectors
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; CHECK: [[REG0:(p[0-9]+)]] = vcmph.eq([[REG1:(r[0-9]+):[0-9]]],[[REG2:(r[0-9]+):[0-9]]])
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; CHECK: [[REG1:(r[0-9]+):[0-9]]] = CONST64(#281479271743489)
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; CHECK: [[REG2:(r[0-9]+):[0-9]]] = mask([[REG0]])
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; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and([[REG2]],[[REG1]])
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define void @compare_vectors(<4 x i16> %a, <4 x i16> %b) {
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entry:
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%result = icmp eq <4 x i16> %a, %b
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call i32 @f.1(<4 x i1> %result)
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ret void
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}
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; CHECK-LABEL: f.1:
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; CHECK: [[REG3:(r[0-9]+)]] = and([[REG3]],##65537)
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; CHECK: [[REG4:(r[0-9]+)]] = and([[REG4]],##65537)
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define i32 @f.1(<4 x i1> %vec) {
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%element = extractelement <4 x i1> %vec, i32 2
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%is_true = icmp eq i1 %element, true
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br i1 %is_true, label %if_true, label %if_false
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if_true:
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call void @action_if_true()
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br label %end
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if_false:
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call void @action_if_false()
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br label %end
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end:
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%result = phi i32 [1, %if_true], [0, %if_false]
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ret i32 %result
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}
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declare void @action_if_true()
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declare void @action_if_false()
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