Brian Cain 2b952753f8
[hexagon] Add support for llvm.thread.pointer (#148752)
UGP contains the pointer for thread data: 

> The TLS area is accessed at the processor level through the special
register UGP This register is set to the address one location above the
TLS area, which grows downwards from UGP.

From the Hexagon ABI spec -
https://docs.qualcomm.com/bundle/publicresource/80-N2040-23_REV_K_Qualcomm_Hexagon_Application_Binary_Interface_User_Guide.pdf

Also: disable clang-format for `NodeType` enum in
`llvm/lib/Target/Hexagon/HexagonISelLowering.h` to avoid disruptive
formatting.
2025-07-15 09:59:04 -05:00

17 lines
539 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=hexagon < %s | FileCheck %s
;
; This test verifies the thread pointer intrinsic implementation for Hexagon.
; The thread pointer (UGP register) is used to access thread-local storage.
declare ptr @llvm.thread.pointer() nounwind readnone
define ptr @thread_pointer() nounwind {
; CHECK-LABEL: thread_pointer:
; CHECK: // %bb.0:
; CHECK: r0 = ugp
; CHECK-NEXT: jumpr r31
%1 = tail call ptr @llvm.thread.pointer()
ret ptr %1
}