2208c97c1b
Similar to 806761a7629df268c8aed49657aeccffa6bca449 -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly.
91 lines
2.5 KiB
LLVM
91 lines
2.5 KiB
LLVM
; RUN: llc -mtriple=hexagon < %s | FileCheck %s
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target triple = "hexagon"
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; CHECK-LABEL: f0:
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; CHECK: r{{[0-9]+}} = cmpyiwh(r{{[0-9]}}:{{[0-9]}},r{{[0-9]+}}*):<<1:rnd:sat
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define i32 @f0(double %a0) {
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b0:
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%v0 = alloca i8, align 1
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%v1 = fptosi double %a0 to i64
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%v2 = tail call i32 @llvm.hexagon.M4.cmpyi.whc(i64 %v1, i32 512)
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%v3 = trunc i32 %v2 to i8
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store volatile i8 %v3, ptr %v0, align 1
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%v4 = load volatile i8, ptr %v0, align 1
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%v5 = zext i8 %v4 to i32
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ret i32 %v5
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.M4.cmpyi.whc(i64, i32) #0
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; CHECK-LABEL: f1:
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; CHECK: r{{[0-9]+}} = cmpyrwh(r{{[0-9]}}:{{[0-9]}},r{{[0-9]+}}*):<<1:rnd:sat
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define i32 @f1(double %a0) {
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b0:
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%v0 = alloca i8, align 1
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%v1 = fptosi double %a0 to i64
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%v2 = tail call i32 @llvm.hexagon.M4.cmpyr.whc(i64 %v1, i32 512)
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%v3 = trunc i32 %v2 to i8
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store volatile i8 %v3, ptr %v0, align 1
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%v4 = load volatile i8, ptr %v0, align 1
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%v5 = zext i8 %v4 to i32
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ret i32 %v5
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.M4.cmpyr.whc(i64, i32) #0
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; CHECK-LABEL: f2:
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; CHECK: r{{[0-9]+}} = popcount(r{{[0-9]}}:{{[0-9]}})
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define i32 @f2(double %a0) {
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b0:
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%v0 = alloca i8, align 1
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%v1 = fptosi double %a0 to i64
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%v2 = tail call i32 @llvm.hexagon.S5.popcountp(i64 %v1)
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%v3 = trunc i32 %v2 to i8
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store volatile i8 %v3, ptr %v0, align 1
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%v4 = load volatile i8, ptr %v0, align 1
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%v5 = zext i8 %v4 to i32
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ret i32 %v5
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.S5.popcountp(i64) #0
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; CHECK-LABEL: f3:
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; CHECK: p{{[0-3]+}} = sfclass(r{{[0-9]}},#3)
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define i32 @f3(float %a0) {
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b0:
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%v0 = alloca i8, align 1
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%v1 = tail call i32 @llvm.hexagon.F2.sfclass(float %a0, i32 3)
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%v2 = trunc i32 %v1 to i8
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store volatile i8 %v2, ptr %v0, align 1
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%v3 = load volatile i8, ptr %v0, align 1
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%v4 = zext i8 %v3 to i32
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ret i32 %v4
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}
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; Function Attrs: readnone
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declare i32 @llvm.hexagon.F2.sfclass(float, i32) #1
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; CHECK-LABEL: f4:
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; CHECK: r{{[0-9]+}} = vasrhub(r{{[0-9]}}:{{[0-9]}},#3):sat
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define i32 @f4(float %a0) {
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b0:
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%v0 = alloca i8, align 1
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%v1 = fptosi float %a0 to i64
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%v2 = tail call i32 @llvm.hexagon.S5.asrhub.sat(i64 %v1, i32 3)
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%v3 = trunc i32 %v2 to i8
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store volatile i8 %v3, ptr %v0, align 1
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%v4 = load volatile i8, ptr %v0, align 1
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%v5 = zext i8 %v4 to i32
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ret i32 %v5
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.S5.asrhub.sat(i64, i32) #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { readnone }
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