2208c97c1b
Similar to 806761a7629df268c8aed49657aeccffa6bca449 -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly.
34 lines
983 B
LLVM
34 lines
983 B
LLVM
; RUN: llc -mtriple=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s
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; CHECK: vmemu(r{{[0-9]}}+#0) = v{{[0-9]*}}
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target triple = "hexagon"
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; Function Attrs: nounwind
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define void @f0(ptr %a0, ptr %a1) #0 {
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b0:
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%v0 = alloca ptr, align 4
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%v1 = alloca ptr, align 4
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%v2 = alloca <16 x i32>, align 64
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store ptr %a0, ptr %v0, align 4
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store ptr %a1, ptr %v1, align 4
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%v3 = load ptr, ptr %v0, align 4
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%v4 = load <16 x i32>, ptr %v2, align 64
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call void asm sideeffect " $1 = vmemu($0);\0A", "r,v"(ptr %v3, <16 x i32> %v4) #1, !srcloc !0
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%v5 = load ptr, ptr %v1, align 4
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%v6 = load <16 x i32>, ptr %v2, align 64
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call void asm sideeffect " vmemu($0) = $1;\0A", "r,v,~{memory}"(ptr %v5, <16 x i32> %v6) #1, !srcloc !1
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ret void
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}
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; Function Attrs: nounwind
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define i32 @f1() #0 {
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b0:
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ret i32 0
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind }
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!0 = !{i32 233}
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!1 = !{i32 307}
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