2208c97c1b
Similar to 806761a7629df268c8aed49657aeccffa6bca449 -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly.
98 lines
3.5 KiB
LLVM
98 lines
3.5 KiB
LLVM
; Check the memd loads are generated by HexagonLoadStoreWidening pass
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; Check that memw loads from adjacent memory location are replaced with memd,
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; though the load/stores alias with instructions that occur later in the block.
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; The order of memory operations remains unchanged.
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; RUN: llc -mtriple=hexagon -verify-machineinstrs < %s | FileCheck %s
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target triple = "hexagon"
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; CHECK-LABEL: load_store_interleaved:
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; CHECK: r{{[0-9]+}}:{{[0-9]+}} = memd(r{{[0-9]+}}+#0)
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; CHECK: memd(r{{[0-9]+}}+#0) = r{{[0-9]+}}:{{[0-9]+}}
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; Function Attrs: mustprogress nounwind
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define linkonce_odr dso_local void @load_store_interleaved(ptr %p, float %a, float %b) local_unnamed_addr {
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entry:
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%0 = load float, ptr %p, align 8
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%add0 = fadd float %0, %a
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store float %add0, ptr %p, align 8
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%q = getelementptr i8, ptr %p, i32 4
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%1 = load float, ptr %q, align 4
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%add1 = fadd float %1, %b
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store float %add1, ptr %q, align 4
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ret void
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}
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; Store can be widened here, but this order of instructions is not currently handled
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; CHECK-LABEL: loads_between_stores:
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; CHECK: r{{[0-9]+}}:{{[0-9]+}} = memd(r{{[0-9]+}}+#0)
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; CHECK-NOT: memd(r{{[0-9]+}}+#4) = r{{[0-9]+}}:{{[0-9]+}}
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; Function Attrs: mustprogress nounwind
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define linkonce_odr dso_local void @loads_between_stores(ptr %p, float %a, float %b) local_unnamed_addr {
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entry:
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%add0 = fadd float %b, %a
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%q = getelementptr i8, ptr %p, i32 4
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%r = getelementptr i8, ptr %p, i32 8
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store float %add0, ptr %r, align 4
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%0 = load float, ptr %p, align 8
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%1 = load float, ptr %q, align 4
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%add1 = fadd float %1, %0
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store float %add1, ptr %q, align 8
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ret void
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}
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; CHECK-LABEL: loads_before_stores:
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; CHECK: r{{[0-9]+}}:{{[0-9]+}} = memd(r{{[0-9]+}}+#0)
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; CHECK: memd(r{{[0-9]+}}+#0) = r{{[0-9]+}}:{{[0-9]+}}
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; Function Attrs: mustprogress nounwind
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define linkonce_odr dso_local void @loads_before_stores(ptr %p, float %a, float %b) local_unnamed_addr {
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entry:
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%0 = load float, ptr %p, align 8
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%q = getelementptr i8, ptr %p, i32 4
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%1 = load float, ptr %q, align 4
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%add0 = fadd float %0, %a
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store float %add0, ptr %p, align 8
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%add1 = fadd float %1, %b
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store float %add1, ptr %q, align 4
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ret void
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}
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; Store can be widened here, but this order of instructions is not currently handled
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; CHECK-LABEL: store_load_interleaved:
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; CHECK: r{{[0-9]+}}:{{[0-9]+}} = memd(r{{[0-9]+}}+#0)
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; CHECK-NOT: memd(r{{[0-9]+}}+#0) = r{{[0-9]+}}:{{[0-9]+}}
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; Function Attrs: mustprogress nounwind
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define linkonce_odr dso_local void @store_load_interleaved(ptr %p, float %a, float %b, float %f) local_unnamed_addr {
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entry:
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%q = getelementptr i8, ptr %p, i32 4
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%r = getelementptr i8, ptr %p, i32 8
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store float %f, ptr %r, align 4
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%0 = load float, ptr %p, align 8
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%add0 = fadd float %0, %a
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store float %add0, ptr %p, align 8
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%1 = load float, ptr %q, align 4
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%add1 = fadd float %1, %b
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%add2 = fadd float %add1, %add0
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store float %add2, ptr %q, align 8
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ret void
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}
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; CHECK-LABEL: stores_between_loads:
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; CHECK-NOT: r{{[0-9]+}}:{{[0-9]+}} = memd(r{{[0-9]+}}+#0)
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; CHECK: memd(r{{[0-9]+}}+#0) = r{{[0-9]+}}:{{[0-9]+}}
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; Function Attrs: mustprogress nounwind
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define linkonce_odr dso_local void @stores_between_loads(ptr %p, float %a, float %b, float %f) local_unnamed_addr {
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entry:
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%0 = load float, ptr %p, align 8
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%add0 = fadd float %f, %0
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store float %add0, ptr %p, align 8
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%q = getelementptr i8, ptr %p, i32 4
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%add1 = fadd float %f, %b
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store float %add1, ptr %q, align 8
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%r = getelementptr i8, ptr %p, i32 8
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%1 = load float, ptr %r, align 4
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%add2 = fadd float %add1, %1
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store float %add2, ptr %r, align 4
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ret void
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}
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