689342de25
This patch adds support for the `q` constraint: a general-purpose register except for $r0 and $r1 (for the csrxchg instruction) Link: https://gcc.gnu.org/pipermail/gcc-patches/2025-May/684339.html
22 lines
749 B
LLVM
22 lines
749 B
LLVM
; RUN: llc --mtriple=loongarch32 --mattr=+f --verify-machineinstrs < %s | FileCheck %s
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; RUN: llc --mtriple=loongarch64 --mattr=+f --verify-machineinstrs < %s | FileCheck %s
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;; Check that the "q" operand is not R0.
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define i32 @constraint_q_not_r0() {
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; CHECK-NOT: csrxchg ${{[a-z]*}}, $r0, 0
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; CHECK-NOT: csrxchg ${{[a-z]*}}, $zero, 0
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entry:
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%2 = tail call i32 asm "csrxchg $0, $1, 0", "=r,q,0"(i32 0, i32 0)
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ret i32 %2
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}
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;; Check that the "q" operand is not R1.
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define i32 @constraint_q_not_r1(i32 %0) {
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; CHECK-NOT: csrxchg ${{[a-z]*}}, $r1, 0
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; CHECK-NOT: csrxchg ${{[a-z]*}}, $ra, 0
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entry:
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%2 = tail call i32 asm "", "={$r1},{$r1}"(i32 0)
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%3 = tail call i32 asm "csrxchg $0, $1, 0", "=r,q,0"(i32 %2, i32 %0)
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ret i32 %3
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}
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