236 lines
7.1 KiB
LLVM
236 lines
7.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s
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define void @load_zext_2i8_to_2i64(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_zext_2i8_to_2i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ld.h $a0, $a0, 0
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; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
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; CHECK-NEXT: vrepli.b $vr1, 0
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; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr0
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; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0
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; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <2 x i8>, ptr %ptr
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%B = zext <2 x i8> %A to <2 x i64>
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store <2 x i64> %B, ptr %dst
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ret void
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}
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define void @load_zext_4i8_to_4i32(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_zext_4i8_to_4i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ld.w $a0, $a0, 0
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; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
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; CHECK-NEXT: vrepli.b $vr1, 0
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; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr0
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; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <4 x i8>, ptr %ptr
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%B = zext <4 x i8> %A to <4 x i32>
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store <4 x i32> %B, ptr %dst
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ret void
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}
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define void @load_zext_8i8_to_8i16(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_zext_8i8_to_8i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ld.d $a0, $a0, 0
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; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
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; CHECK-NEXT: vrepli.b $vr1, 0
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; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <8 x i8>, ptr %ptr
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%B = zext <8 x i8> %A to <8 x i16>
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store <8 x i16> %B, ptr %dst
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ret void
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}
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define void @load_zext_2i16_to_2i64(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_zext_2i16_to_2i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ld.w $a0, $a0, 0
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; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
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; CHECK-NEXT: vrepli.b $vr1, 0
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; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0
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; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <2 x i16>, ptr %ptr
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%B = zext <2 x i16> %A to <2 x i64>
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store <2 x i64> %B, ptr %dst
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ret void
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}
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define void @load_zext_4i16_to_4i32(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_zext_4i16_to_4i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ld.d $a0, $a0, 0
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; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
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; CHECK-NEXT: vrepli.b $vr1, 0
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; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <4 x i16>, ptr %ptr
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%B = zext <4 x i16> %A to <4 x i32>
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store <4 x i32> %B, ptr %dst
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ret void
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}
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define void @load_zext_2i32_to_2i64(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_zext_2i32_to_2i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ld.d $a0, $a0, 0
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; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
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; CHECK-NEXT: vrepli.b $vr1, 0
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; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <2 x i32>, ptr %ptr
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%B = zext <2 x i32> %A to <2 x i64>
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store <2 x i64> %B, ptr %dst
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ret void
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}
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define void @load_zext_16i8_to_16i16(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_zext_16i8_to_16i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a0, 0
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; CHECK-NEXT: vrepli.b $vr1, 0
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; CHECK-NEXT: vilvl.b $vr2, $vr1, $vr0
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; CHECK-NEXT: vilvh.b $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a1, 16
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; CHECK-NEXT: vst $vr2, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <16 x i8>, ptr %ptr
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%B = zext <16 x i8> %A to <16 x i16>
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store <16 x i16> %B, ptr %dst
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ret void
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}
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define void @load_zext_16i8_to_16i32(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_zext_16i8_to_16i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a0, 0
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; CHECK-NEXT: vrepli.b $vr1, 0
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; CHECK-NEXT: vilvl.b $vr2, $vr1, $vr0
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; CHECK-NEXT: vilvl.h $vr3, $vr1, $vr2
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; CHECK-NEXT: vilvh.h $vr2, $vr1, $vr2
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; CHECK-NEXT: vilvh.b $vr0, $vr1, $vr0
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; CHECK-NEXT: vilvl.h $vr4, $vr1, $vr0
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; CHECK-NEXT: vilvh.h $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a1, 48
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; CHECK-NEXT: vst $vr4, $a1, 32
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; CHECK-NEXT: vst $vr2, $a1, 16
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; CHECK-NEXT: vst $vr3, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <16 x i8>, ptr %ptr
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%B = zext <16 x i8> %A to <16 x i32>
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store <16 x i32> %B, ptr %dst
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ret void
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}
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define void @load_zext_16i8_to_16i64(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_zext_16i8_to_16i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a0, 0
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; CHECK-NEXT: vrepli.b $vr1, 0
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; CHECK-NEXT: vilvl.b $vr2, $vr1, $vr0
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; CHECK-NEXT: vilvl.h $vr3, $vr1, $vr2
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; CHECK-NEXT: vilvl.w $vr4, $vr1, $vr3
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; CHECK-NEXT: vilvh.w $vr3, $vr1, $vr3
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; CHECK-NEXT: vilvh.h $vr2, $vr1, $vr2
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; CHECK-NEXT: vilvl.w $vr5, $vr1, $vr2
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; CHECK-NEXT: vilvh.w $vr2, $vr1, $vr2
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; CHECK-NEXT: vilvh.b $vr0, $vr1, $vr0
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; CHECK-NEXT: vilvl.h $vr6, $vr1, $vr0
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; CHECK-NEXT: vilvl.w $vr7, $vr1, $vr6
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; CHECK-NEXT: vilvh.w $vr6, $vr1, $vr6
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; CHECK-NEXT: vilvh.h $vr0, $vr1, $vr0
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; CHECK-NEXT: vilvl.w $vr8, $vr1, $vr0
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; CHECK-NEXT: vilvh.w $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a1, 112
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; CHECK-NEXT: vst $vr8, $a1, 96
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; CHECK-NEXT: vst $vr6, $a1, 80
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; CHECK-NEXT: vst $vr7, $a1, 64
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; CHECK-NEXT: vst $vr2, $a1, 48
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; CHECK-NEXT: vst $vr5, $a1, 32
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; CHECK-NEXT: vst $vr3, $a1, 16
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; CHECK-NEXT: vst $vr4, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <16 x i8>, ptr %ptr
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%B = zext <16 x i8> %A to <16 x i64>
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store <16 x i64> %B, ptr %dst
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ret void
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}
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define void @load_zext_8i16_to_8i32(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_zext_8i16_to_8i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a0, 0
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; CHECK-NEXT: vrepli.b $vr1, 0
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; CHECK-NEXT: vilvl.h $vr2, $vr1, $vr0
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; CHECK-NEXT: vilvh.h $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a1, 16
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; CHECK-NEXT: vst $vr2, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <8 x i16>, ptr %ptr
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%B = zext <8 x i16> %A to <8 x i32>
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store <8 x i32> %B, ptr %dst
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ret void
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}
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define void @load_zext_8i16_to_8i64(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_zext_8i16_to_8i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a0, 0
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; CHECK-NEXT: vrepli.b $vr1, 0
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; CHECK-NEXT: vilvl.h $vr2, $vr1, $vr0
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; CHECK-NEXT: vilvl.w $vr3, $vr1, $vr2
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; CHECK-NEXT: vilvh.w $vr2, $vr1, $vr2
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; CHECK-NEXT: vilvh.h $vr0, $vr1, $vr0
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; CHECK-NEXT: vilvl.w $vr4, $vr1, $vr0
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; CHECK-NEXT: vilvh.w $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a1, 48
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; CHECK-NEXT: vst $vr4, $a1, 32
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; CHECK-NEXT: vst $vr2, $a1, 16
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; CHECK-NEXT: vst $vr3, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <8 x i16>, ptr %ptr
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%B = zext <8 x i16> %A to <8 x i64>
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store <8 x i64> %B, ptr %dst
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ret void
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}
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define void @load_zext_4i32_to_4i64(ptr %ptr, ptr %dst) {
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; CHECK-LABEL: load_zext_4i32_to_4i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a0, 0
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; CHECK-NEXT: vrepli.b $vr1, 0
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; CHECK-NEXT: vilvl.w $vr2, $vr1, $vr0
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; CHECK-NEXT: vilvh.w $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a1, 16
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; CHECK-NEXT: vst $vr2, $a1, 0
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; CHECK-NEXT: ret
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entry:
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%A = load <4 x i32>, ptr %ptr
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%B = zext <4 x i32> %A to <4 x i64>
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store <4 x i64> %B, ptr %dst
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ret void
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}
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