307d1249ea
ucmp can be promoted with either sext or zext. RISC-V and LoongArch prefer sext for promoting i32 to i64 unless the inputs are known to be zero extended already. This patch uses the existing SExtOrZExtPromotedOperands function that is used by SETCC promotion to intelligently handle this.
105 lines
3.0 KiB
LLVM
105 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=loongarch64 -mattr=+d --verify-machineinstrs < %s | FileCheck %s
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define i8 @ucmp.8.8(i8 zeroext %x, i8 zeroext %y) nounwind {
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; CHECK-LABEL: ucmp.8.8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sltu $a2, $a0, $a1
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; CHECK-NEXT: sltu $a0, $a1, $a0
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; CHECK-NEXT: sub.d $a0, $a0, $a2
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; CHECK-NEXT: ret
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%1 = call i8 @llvm.ucmp(i8 %x, i8 %y)
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ret i8 %1
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}
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define i8 @ucmp.8.16(i16 zeroext %x, i16 zeroext %y) nounwind {
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; CHECK-LABEL: ucmp.8.16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sltu $a2, $a0, $a1
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; CHECK-NEXT: sltu $a0, $a1, $a0
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; CHECK-NEXT: sub.d $a0, $a0, $a2
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; CHECK-NEXT: ret
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%1 = call i8 @llvm.ucmp(i16 %x, i16 %y)
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ret i8 %1
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}
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define i8 @ucmp.8.32(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: ucmp.8.32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi.w $a1, $a1, 0
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; CHECK-NEXT: addi.w $a0, $a0, 0
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; CHECK-NEXT: sltu $a2, $a0, $a1
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; CHECK-NEXT: sltu $a0, $a1, $a0
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; CHECK-NEXT: sub.d $a0, $a0, $a2
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; CHECK-NEXT: ret
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%1 = call i8 @llvm.ucmp(i32 %x, i32 %y)
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ret i8 %1
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}
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define i8 @ucmp.8.64(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: ucmp.8.64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sltu $a2, $a0, $a1
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; CHECK-NEXT: sltu $a0, $a1, $a0
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; CHECK-NEXT: sub.d $a0, $a0, $a2
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; CHECK-NEXT: ret
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%1 = call i8 @llvm.ucmp(i64 %x, i64 %y)
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ret i8 %1
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}
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define i8 @ucmp.8.128(i128 %x, i128 %y) nounwind {
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; CHECK-LABEL: ucmp.8.128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sltu $a4, $a1, $a3
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; CHECK-NEXT: xor $a5, $a1, $a3
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; CHECK-NEXT: sltui $a5, $a5, 1
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; CHECK-NEXT: masknez $a4, $a4, $a5
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; CHECK-NEXT: sltu $a6, $a0, $a2
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; CHECK-NEXT: maskeqz $a6, $a6, $a5
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; CHECK-NEXT: or $a4, $a6, $a4
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; CHECK-NEXT: sltu $a1, $a3, $a1
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; CHECK-NEXT: masknez $a1, $a1, $a5
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; CHECK-NEXT: sltu $a0, $a2, $a0
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; CHECK-NEXT: maskeqz $a0, $a0, $a5
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; CHECK-NEXT: or $a0, $a0, $a1
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; CHECK-NEXT: sub.d $a0, $a0, $a4
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; CHECK-NEXT: ret
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%1 = call i8 @llvm.ucmp(i128 %x, i128 %y)
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ret i8 %1
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}
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define i32 @ucmp.32.32(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: ucmp.32.32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi.w $a1, $a1, 0
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; CHECK-NEXT: addi.w $a0, $a0, 0
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; CHECK-NEXT: sltu $a2, $a0, $a1
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; CHECK-NEXT: sltu $a0, $a1, $a0
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; CHECK-NEXT: sub.d $a0, $a0, $a2
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; CHECK-NEXT: ret
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%1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
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ret i32 %1
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}
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define i32 @ucmp.32.64(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: ucmp.32.64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sltu $a2, $a0, $a1
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; CHECK-NEXT: sltu $a0, $a1, $a0
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; CHECK-NEXT: sub.d $a0, $a0, $a2
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; CHECK-NEXT: ret
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%1 = call i32 @llvm.ucmp(i64 %x, i64 %y)
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ret i32 %1
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}
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define i64 @ucmp.64.64(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: ucmp.64.64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sltu $a2, $a0, $a1
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; CHECK-NEXT: sltu $a0, $a1, $a0
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; CHECK-NEXT: sub.d $a0, $a0, $a2
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; CHECK-NEXT: ret
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%1 = call i64 @llvm.ucmp(i64 %x, i64 %y)
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ret i64 %1
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}
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