c4c9d4f306
Add support for the moveq instruction, which is both faster and smaller (1/2 to 1/3 the size) than a move with immediate to register. This change introduces the instruction, along with a set of pseudoinstructions to handle immediate moves to a register that is lowered post-RA. Pseudos are used as moveq can only write to the full register, which makes matching i8 and i16 immediate loads difficult in tablegen. Furthermore, selecting moveq before RA constrains that immediate to be moved into a data register, which may not be optimal. The bulk of this change are fixes to existing tests, which cover the new functionality sufficiently.
34 lines
833 B
LLVM
34 lines
833 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s
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define i1 @t1(i64 %x) nounwind {
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; CHECK-LABEL: t1:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: moveq #31, %d1
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; CHECK-NEXT: move.l (4,%sp), %d0
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; CHECK-NEXT: lsr.l %d1, %d0
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; CHECK-NEXT: ; kill: def $bd0 killed $bd0 killed $d0
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; CHECK-NEXT: rts
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%B = icmp slt i64 %x, 0
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ret i1 %B
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}
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define i1 @t2(i64 %x) nounwind {
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; CHECK-LABEL: t2:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: cmpi.l #0, (4,%sp)
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; CHECK-NEXT: seq %d0
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; CHECK-NEXT: rts
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%tmp = icmp ult i64 %x, 4294967296
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ret i1 %tmp
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}
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define i1 @t3(i32 %x) nounwind {
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; CHECK-LABEL: t3:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: moveq #0, %d0
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; CHECK-NEXT: rts
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%tmp = icmp ugt i32 %x, -1
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ret i1 %tmp
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}
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