d3c10b51a9
Add three more special cases for loading registers with immediates. The first allows values in the range of [-255, 255] to be loaded with MOVEQ, even if the register is more than 8 bits and the sign extention is unwanted. This is done by loading the bitwise complement of the desired value, then performing a NOT instruction on the loaded register. This special case is only used when a simple MOVEQ cannot be used, and is only used for 32 bit data registers. Address registers cannot support MOVEQ, and the two-instruction sequence is no faster or smaller than a plain MOVE instruction when loading 16 bit immediates on the 68000, and likely slower for more sophisticated microarchitectures. However, the instruction sequence is both smaller and faster than the corresponding MOVE instruction for 32 bit register widths. The second special case is for zeroing address registers. This simply expands to subtracting a register with itself, consuming one instruction word rather than 2-3, with a small improvement in speed as well. The last special case is for assigning sign-extended 16-bit values to a full address register. This takes advantage of the fact that the movea.w instruction sign extends the output, permitting the immediate to be smaller. This is similar to using lea with a 16-bit address, which is not added in this patch as 16-bit absolute addressing is not yet implemented. This is a v2 submission of #90817. It also creates a 'Data' test directory to better align with the backend's tablegen layout.
130 lines
3.8 KiB
LLVM
130 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -frame-pointer=all -mtriple=m68k %s -verify-machineinstrs -o - \
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; RUN: | FileCheck --check-prefix=FP %s
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; RUN: llc -frame-pointer=none -mtriple=m68k %s -verify-machineinstrs -o - \
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; RUN: | FileCheck --check-prefix=NO-FP %s
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define i32 @fib(i32 %a, i32 %b) {
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; FP-LABEL: fib:
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; FP: .cfi_startproc
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; FP-NEXT: ; %bb.0: ; %entry
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; FP-NEXT: link.w %a6, #-32
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; FP-NEXT: .cfi_def_cfa_offset -8
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; FP-NEXT: .cfi_offset %a6, -8
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; FP-NEXT: .cfi_def_cfa_register %a6
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; FP-NEXT: move.l (8,%a6), %d1
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; FP-NEXT: move.l %d1, (-32,%a6)
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; FP-NEXT: move.l (12,%a6), %d0
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; FP-NEXT: add.l %d0, %d1
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; FP-NEXT: move.l %d0, (-28,%a6)
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; FP-NEXT: add.l %d1, %d0
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; FP-NEXT: move.l %d1, (-24,%a6)
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; FP-NEXT: add.l %d0, %d1
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; FP-NEXT: move.l %d0, (-20,%a6)
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; FP-NEXT: move.l %d1, (-16,%a6)
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; FP-NEXT: add.l %d1, %d0
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; FP-NEXT: move.l %d0, (-12,%a6)
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; FP-NEXT: add.l %d0, %d1
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; FP-NEXT: move.l %d1, (-8,%a6)
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; FP-NEXT: add.l %d1, %d0
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; FP-NEXT: move.l %d0, (-4,%a6)
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; FP-NEXT: unlk %a6
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; FP-NEXT: rts
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;
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; NO-FP-LABEL: fib:
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; NO-FP: .cfi_startproc
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; NO-FP-NEXT: ; %bb.0: ; %entry
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; NO-FP-NEXT: suba.l #32, %sp
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; NO-FP-NEXT: .cfi_def_cfa_offset -36
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; NO-FP-NEXT: move.l (36,%sp), %d1
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; NO-FP-NEXT: move.l %d1, (0,%sp)
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; NO-FP-NEXT: move.l (40,%sp), %d0
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; NO-FP-NEXT: add.l %d0, %d1
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; NO-FP-NEXT: move.l %d0, (4,%sp)
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; NO-FP-NEXT: add.l %d1, %d0
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; NO-FP-NEXT: move.l %d1, (8,%sp)
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; NO-FP-NEXT: add.l %d0, %d1
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; NO-FP-NEXT: move.l %d0, (12,%sp)
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; NO-FP-NEXT: move.l %d1, (16,%sp)
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; NO-FP-NEXT: add.l %d1, %d0
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; NO-FP-NEXT: move.l %d0, (20,%sp)
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; NO-FP-NEXT: add.l %d0, %d1
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; NO-FP-NEXT: move.l %d1, (24,%sp)
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; NO-FP-NEXT: add.l %d1, %d0
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; NO-FP-NEXT: move.l %d0, (28,%sp)
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; NO-FP-NEXT: adda.l #32, %sp
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; NO-FP-NEXT: rts
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entry:
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%arr = alloca [8 x i32], align 4
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%s0 = getelementptr i32, ptr %arr, i32 0
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%s1 = getelementptr i32, ptr %arr, i32 1
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store i32 %a, ptr %s0
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store i32 %b, ptr %s1
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%ptr0 = getelementptr i32, ptr %arr, i32 0
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%ptr1 = getelementptr i32, ptr %arr, i32 1
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%ptr2 = getelementptr i32, ptr %arr, i32 2
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%ptr3 = getelementptr i32, ptr %arr, i32 3
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%ptr4 = getelementptr i32, ptr %arr, i32 4
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%ptr5 = getelementptr i32, ptr %arr, i32 5
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%ptr6 = getelementptr i32, ptr %arr, i32 6
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%ptr7 = getelementptr i32, ptr %arr, i32 7
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%res0 = load i32, ptr %ptr0
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%res1 = load i32, ptr %ptr1
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%res2 = add i32 %res0, %res1
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store i32 %res2, ptr %ptr2
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%res3 = add i32 %res1, %res2
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store i32 %res3, ptr %ptr3
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%res4 = add i32 %res2, %res3
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store i32 %res4, ptr %ptr4
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%res5 = add i32 %res3, %res4
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store i32 %res5, ptr %ptr5
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%res6 = add i32 %res4, %res5
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store i32 %res6, ptr %ptr6
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%res7 = add i32 %res5, %res6
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store i32 %res7, ptr %ptr7
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ret i32 %res7
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}
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define i32 @test_gep() {
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; FP-LABEL: test_gep:
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; FP: .cfi_startproc
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; FP-NEXT: ; %bb.0: ; %entry
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; FP-NEXT: link.w %a6, #-256
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; FP-NEXT: .cfi_def_cfa_offset -8
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; FP-NEXT: .cfi_offset %a6, -8
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; FP-NEXT: .cfi_def_cfa_register %a6
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; FP-NEXT: move.l #21, (-4,%a6)
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; FP-NEXT: move.l #12, (-256,%a6)
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; FP-NEXT: moveq #0, %d0
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; FP-NEXT: unlk %a6
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; FP-NEXT: rts
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;
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; NO-FP-LABEL: test_gep:
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; NO-FP: .cfi_startproc
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; NO-FP-NEXT: ; %bb.0: ; %entry
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; NO-FP-NEXT: suba.l #256, %sp
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; NO-FP-NEXT: .cfi_def_cfa_offset -260
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; NO-FP-NEXT: move.l #21, (252,%sp)
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; NO-FP-NEXT: move.l #12, (0,%sp)
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; NO-FP-NEXT: moveq #0, %d0
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; NO-FP-NEXT: adda.l #256, %sp
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; NO-FP-NEXT: rts
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entry:
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%arr = alloca [8 x [8 x i32]]
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%ptr1 = getelementptr [8 x i32], ptr %arr, i64 0, i64 0
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store i32 12, ptr %ptr1
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%ptr2 = getelementptr [8 x i32], ptr %arr, i64 7, i64 7
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store i32 21, ptr %ptr2
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ret i32 0
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}
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