4d629f9744
In review of bbde6b, I had originally proposed that we support the legacy text format. As review evolved, it bacame clear this had been a bad idea (too much complexity), but in order to let that patch finally move forward, I approved the change with the variant. This change undoes the variant, and updates all the tests to just use the array form.
237 lines
7.1 KiB
YAML
237 lines
7.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion | FileCheck %s --check-prefix=R6
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# RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion -relocation-model=pic | FileCheck %s --check-prefix=PIC
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# Test the long branch expansion of various branches
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--- |
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define i32 @a(double %a, double %b) {
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entry:
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%cmp = fcmp une double %a, %b
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br i1 %cmp, label %if.then, label %return
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if.then: ; preds = %entry
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call void asm sideeffect ".space 310680", "~{$1}"()
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ret i32 0
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return: ; preds = %entry
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ret i32 1
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}
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define i32 @b(double %a, double %b) {
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entry:
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%cmp = fcmp ueq double %a, %b
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br i1 %cmp, label %if.then, label %return
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if.then: ; preds = %entry
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call void asm sideeffect ".space 310680", "~{$1}"()
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ret i32 0
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return: ; preds = %entry
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ret i32 1
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}
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...
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---
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name: a
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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registers:
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liveins:
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- { reg: '$d12_64', virtual-reg: '' }
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- { reg: '$d14_64', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: []
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restorePoint: []
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fixedStack:
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stack:
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constants:
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body: |
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; R6-LABEL: name: a
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; R6: bb.0.entry:
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; R6: successors: %bb.2(0x50000000), %bb.1(0x30000000)
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; R6: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
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; R6: BC1NEZ $d0_64, %bb.2 {
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; R6: $zero = SLL $zero, 0
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; R6: }
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; R6: bb.1.entry:
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; R6: successors: %bb.3(0x80000000)
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; R6: BC %bb.3
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; R6: bb.2.if.then:
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; R6: INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
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; R6: PseudoReturn undef $ra, implicit killed $v0 {
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; R6: $v0 = ADDiu $zero, 0
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; R6: }
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; R6: bb.3.return:
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; R6: PseudoReturn undef $ra, implicit killed $v0 {
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; R6: $v0 = ADDiu $zero, 1
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; R6: }
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; PIC-LABEL: name: a
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; PIC: bb.0.entry:
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; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
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; PIC: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
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; PIC: BC1NEZ $d0_64, %bb.3 {
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; PIC: $zero = SLL $zero, 0
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; PIC: }
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; PIC: bb.1.entry:
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; PIC: successors: %bb.2(0x80000000)
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; PIC: $sp = ADDiu $sp, -8
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; PIC: SW $ra, $sp, 0
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; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
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; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
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; PIC: BALC %bb.2, implicit-def $ra
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; PIC: bb.2.entry:
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; PIC: successors: %bb.4(0x80000000)
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; PIC: $at = ADDu $ra, $at
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; PIC: $ra = LW $sp, 0
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; PIC: $sp = ADDiu $sp, 8
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; PIC: JIC $at, 0, implicit-def $at
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; PIC: bb.3.if.then:
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; PIC: INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
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; PIC: PseudoReturn undef $ra, implicit killed $v0 {
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; PIC: $v0 = ADDiu $zero, 0
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; PIC: }
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; PIC: bb.4.return:
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; PIC: PseudoReturn undef $ra, implicit killed $v0 {
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; PIC: $v0 = ADDiu $zero, 1
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; PIC: }
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bb.0.entry:
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successors: %bb.1(0x50000000), %bb.2(0x30000000)
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liveins: $d12_64, $d14_64
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$f0 = CMP_EQ_D killed $d12_64, killed $d14_64
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BC1EQZ killed $d0_64, %bb.2, implicit-def $at
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bb.1.if.then:
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INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
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$v0 = ADDiu $zero, 0
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PseudoReturn undef $ra, implicit killed $v0
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bb.2.return:
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$v0 = ADDiu $zero, 1
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PseudoReturn undef $ra, implicit killed $v0
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...
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---
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name: b
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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registers:
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liveins:
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- { reg: '$d12_64', virtual-reg: '' }
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- { reg: '$d14_64', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: []
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restorePoint: []
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fixedStack:
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stack:
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constants:
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body: |
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; R6-LABEL: name: b
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; R6: bb.0.entry:
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; R6: successors: %bb.2(0x50000000), %bb.1(0x30000000)
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; R6: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
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; R6: BC1EQZ $d0_64, %bb.2 {
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; R6: $zero = SLL $zero, 0
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; R6: }
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; R6: bb.1.entry:
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; R6: successors: %bb.3(0x80000000)
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; R6: BC %bb.3
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; R6: bb.2.if.then:
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; R6: INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
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; R6: PseudoReturn undef $ra, implicit killed $v0 {
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; R6: $v0 = ADDiu $zero, 0
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; R6: }
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; R6: bb.3.return:
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; R6: PseudoReturn undef $ra, implicit killed $v0 {
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; R6: $v0 = ADDiu $zero, 1
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; R6: }
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; PIC-LABEL: name: b
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; PIC: bb.0.entry:
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; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
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; PIC: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
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; PIC: BC1EQZ $d0_64, %bb.3 {
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; PIC: $zero = SLL $zero, 0
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; PIC: }
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; PIC: bb.1.entry:
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; PIC: successors: %bb.2(0x80000000)
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; PIC: $sp = ADDiu $sp, -8
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; PIC: SW $ra, $sp, 0
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; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
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; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
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; PIC: BALC %bb.2, implicit-def $ra
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; PIC: bb.2.entry:
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; PIC: successors: %bb.4(0x80000000)
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; PIC: $at = ADDu $ra, $at
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; PIC: $ra = LW $sp, 0
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; PIC: $sp = ADDiu $sp, 8
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; PIC: JIC $at, 0, implicit-def $at
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; PIC: bb.3.if.then:
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; PIC: INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
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; PIC: PseudoReturn undef $ra, implicit killed $v0 {
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; PIC: $v0 = ADDiu $zero, 0
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; PIC: }
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; PIC: bb.4.return:
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; PIC: PseudoReturn undef $ra, implicit killed $v0 {
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; PIC: $v0 = ADDiu $zero, 1
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; PIC: }
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bb.0.entry:
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successors: %bb.1(0x50000000), %bb.2(0x30000000)
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liveins: $d12_64, $d14_64
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$f0 = CMP_EQ_D killed $d12_64, killed $d14_64
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BC1NEZ killed $d0_64, %bb.2, implicit-def $at
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bb.1.if.then:
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INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
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$v0 = ADDiu $zero, 0
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PseudoReturn undef $ra, implicit killed $v0
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bb.2.return:
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$v0 = ADDiu $zero, 1
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PseudoReturn undef $ra, implicit killed $v0
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...
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