4d629f9744
In review of bbde6b, I had originally proposed that we support the legacy text format. As review evolved, it bacame clear this had been a bad idea (too much complexity), but in order to let that patch finally move forward, I approved the change with the variant. This change undoes the variant, and updates all the tests to just use the array form.
693 lines
20 KiB
YAML
693 lines
20 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=mips64-mti-linux-gnu %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion | FileCheck %s --check-prefix=MIPS64
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# RUN: llc -mtriple=mips64-mti-linux-gnu %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion -relocation-model=pic | FileCheck %s --check-prefix=PIC
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# Test the long branch expansion of various branches
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--- |
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define i64 @expand_BEQ64(i64 %a, i64 %b) {
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%cmp = icmp eq i64 %a, %b
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br i1 %cmp, label %iftrue, label %tail
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iftrue:
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call void asm sideeffect ".space 131068", ""()
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ret i64 1
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tail:
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ret i64 0
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}
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define i64 @expand_BNE64(i64 %a, i64 %b) {
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%cmp = icmp eq i64 %a, %b
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br i1 %cmp, label %iftrue, label %tail
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iftrue:
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call void asm sideeffect ".space 131068", ""()
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ret i64 1
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tail:
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ret i64 0
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}
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define i64 @expand_BGEZ64(i64 %a, i64 %b) {
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%cmp = icmp eq i64 %a, %b
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br i1 %cmp, label %iftrue, label %tail
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iftrue:
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call void asm sideeffect ".space 131068", ""()
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ret i64 1
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tail:
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ret i64 0
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}
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define i64 @expand_BGTZ64(i64 %a, i64 %b) {
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%cmp = icmp eq i64 %a, %b
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br i1 %cmp, label %iftrue, label %tail
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iftrue:
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call void asm sideeffect ".space 131068", ""()
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ret i64 1
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tail:
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ret i64 0
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}
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define i64 @expand_BLEZ64(i64 %a, i64 %b) {
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%cmp = icmp eq i64 %a, %b
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br i1 %cmp, label %iftrue, label %tail
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iftrue:
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call void asm sideeffect ".space 131068", ""()
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ret i64 1
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tail:
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ret i64 0
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}
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define i64 @expand_BLTZ64(i64 %a, i64 %b) {
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%cmp = icmp eq i64 %a, %b
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br i1 %cmp, label %iftrue, label %tail
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iftrue:
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call void asm sideeffect ".space 131068", ""()
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ret i64 1
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tail:
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ret i64 0
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}
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...
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---
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name: expand_BEQ64
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alignment: 8
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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registers:
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liveins:
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- { reg: '$a0_64', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: []
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restorePoint: []
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fixedStack:
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stack:
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constants:
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body: |
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; MIPS64-LABEL: name: expand_BEQ64
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; MIPS64: bb.0 (%ir-block.0):
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; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; MIPS64: BNE64 $a0_64, $zero_64, %bb.2, implicit-def $at {
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; MIPS64: $zero = SLL $zero, 0
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; MIPS64: }
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; MIPS64: bb.1 (%ir-block.0):
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; MIPS64: successors: %bb.3(0x80000000)
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; MIPS64: J %bb.3, implicit-def $at {
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; MIPS64: $zero = SLL $zero, 0
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; MIPS64: }
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; MIPS64: bb.2.iftrue:
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; MIPS64: INLINEASM &".space 131068", 1
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; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
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; MIPS64: $v0_64 = DADDiu $zero_64, 1
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; MIPS64: }
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; MIPS64: bb.3.tail:
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; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
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; MIPS64: $v0_64 = DADDiu $zero_64, 0
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; MIPS64: }
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; PIC-LABEL: name: expand_BEQ64
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; PIC: bb.0 (%ir-block.0):
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; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
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; PIC: BNE64 $a0_64, $zero_64, %bb.3, implicit-def $at {
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; PIC: $zero = SLL $zero, 0
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; PIC: }
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; PIC: bb.1 (%ir-block.0):
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; PIC: successors: %bb.2(0x80000000)
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; PIC: $sp_64 = DADDiu $sp_64, -16
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; PIC: SD $ra_64, $sp_64, 0
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; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
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; PIC: $at_64 = DSLL $at_64, 16
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; PIC: BAL_BR %bb.2, implicit-def $ra {
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; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
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; PIC: }
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; PIC: bb.2 (%ir-block.0):
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; PIC: successors: %bb.4(0x80000000)
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; PIC: $at_64 = DADDu $ra_64, $at_64
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; PIC: $ra_64 = LD $sp_64, 0
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; PIC: JR64 $at_64 {
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; PIC: $sp_64 = DADDiu $sp_64, 16
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; PIC: }
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; PIC: bb.3.iftrue:
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; PIC: INLINEASM &".space 131068", 1
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; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
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; PIC: $v0_64 = DADDiu $zero_64, 1
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; PIC: }
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; PIC: bb.4.tail:
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; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
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; PIC: $v0_64 = DADDiu $zero_64, 0
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; PIC: }
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bb.0 (%ir-block.0):
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $a0_64
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BEQ64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
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bb.1.iftrue:
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INLINEASM &".space 131068", 1
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$v0_64 = DADDiu $zero_64, 1
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PseudoReturn64 undef $ra_64, implicit killed $v0_64
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bb.2.tail:
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$v0_64 = DADDiu $zero_64, 0
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PseudoReturn64 undef $ra_64, implicit killed $v0_64
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...
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---
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name: expand_BNE64
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alignment: 8
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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registers:
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liveins:
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- { reg: '$a0_64', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: []
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restorePoint: []
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fixedStack:
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stack:
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constants:
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body: |
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; MIPS64-LABEL: name: expand_BNE64
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; MIPS64: bb.0 (%ir-block.0):
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; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; MIPS64: BEQ64 $a0_64, $zero_64, %bb.2, implicit-def $at {
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; MIPS64: $zero = SLL $zero, 0
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; MIPS64: }
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; MIPS64: bb.1 (%ir-block.0):
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; MIPS64: successors: %bb.3(0x80000000)
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; MIPS64: J %bb.3, implicit-def $at {
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; MIPS64: $zero = SLL $zero, 0
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; MIPS64: }
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; MIPS64: bb.2.iftrue:
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; MIPS64: INLINEASM &".space 131068", 1
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; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
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; MIPS64: $v0_64 = DADDiu $zero_64, 1
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; MIPS64: }
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; MIPS64: bb.3.tail:
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; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
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; MIPS64: $v0_64 = DADDiu $zero_64, 0
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; MIPS64: }
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; PIC-LABEL: name: expand_BNE64
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; PIC: bb.0 (%ir-block.0):
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; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
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; PIC: BEQ64 $a0_64, $zero_64, %bb.3, implicit-def $at {
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; PIC: $zero = SLL $zero, 0
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; PIC: }
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; PIC: bb.1 (%ir-block.0):
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; PIC: successors: %bb.2(0x80000000)
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; PIC: $sp_64 = DADDiu $sp_64, -16
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; PIC: SD $ra_64, $sp_64, 0
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; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
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; PIC: $at_64 = DSLL $at_64, 16
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; PIC: BAL_BR %bb.2, implicit-def $ra {
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; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
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; PIC: }
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; PIC: bb.2 (%ir-block.0):
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; PIC: successors: %bb.4(0x80000000)
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; PIC: $at_64 = DADDu $ra_64, $at_64
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; PIC: $ra_64 = LD $sp_64, 0
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; PIC: JR64 $at_64 {
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; PIC: $sp_64 = DADDiu $sp_64, 16
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; PIC: }
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; PIC: bb.3.iftrue:
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; PIC: INLINEASM &".space 131068", 1
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; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
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; PIC: $v0_64 = DADDiu $zero_64, 1
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; PIC: }
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; PIC: bb.4.tail:
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; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
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; PIC: $v0_64 = DADDiu $zero_64, 0
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; PIC: }
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bb.0 (%ir-block.0):
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $a0_64
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BNE64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
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bb.1.iftrue:
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INLINEASM &".space 131068", 1
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$v0_64 = DADDiu $zero_64, 1
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PseudoReturn64 undef $ra_64, implicit killed $v0_64
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bb.2.tail:
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$v0_64 = DADDiu $zero_64, 0
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PseudoReturn64 undef $ra_64, implicit killed $v0_64
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...
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---
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name: expand_BGEZ64
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alignment: 8
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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registers:
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liveins:
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- { reg: '$a0_64', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: []
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restorePoint: []
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fixedStack:
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stack:
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constants:
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body: |
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; MIPS64-LABEL: name: expand_BGEZ64
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; MIPS64: bb.0 (%ir-block.0):
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; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; MIPS64: BLTZ64 $a0_64, %bb.2, implicit-def $at {
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; MIPS64: $zero = SLL $zero, 0
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; MIPS64: }
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; MIPS64: bb.1 (%ir-block.0):
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; MIPS64: successors: %bb.3(0x80000000)
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; MIPS64: J %bb.3, implicit-def $at {
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; MIPS64: $zero = SLL $zero, 0
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; MIPS64: }
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; MIPS64: bb.2.iftrue:
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; MIPS64: INLINEASM &".space 131068", 1
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; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
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; MIPS64: $v0_64 = DADDiu $zero_64, 1
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; MIPS64: }
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; MIPS64: bb.3.tail:
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; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
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; MIPS64: $v0_64 = DADDiu $zero_64, 0
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; MIPS64: }
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; PIC-LABEL: name: expand_BGEZ64
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; PIC: bb.0 (%ir-block.0):
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; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
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; PIC: BLTZ64 $a0_64, %bb.3, implicit-def $at {
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; PIC: $zero = SLL $zero, 0
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; PIC: }
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; PIC: bb.1 (%ir-block.0):
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; PIC: successors: %bb.2(0x80000000)
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; PIC: $sp_64 = DADDiu $sp_64, -16
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; PIC: SD $ra_64, $sp_64, 0
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; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
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; PIC: $at_64 = DSLL $at_64, 16
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; PIC: BAL_BR %bb.2, implicit-def $ra {
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; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
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; PIC: }
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; PIC: bb.2 (%ir-block.0):
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; PIC: successors: %bb.4(0x80000000)
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; PIC: $at_64 = DADDu $ra_64, $at_64
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; PIC: $ra_64 = LD $sp_64, 0
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; PIC: JR64 $at_64 {
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; PIC: $sp_64 = DADDiu $sp_64, 16
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; PIC: }
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; PIC: bb.3.iftrue:
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; PIC: INLINEASM &".space 131068", 1
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; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
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; PIC: $v0_64 = DADDiu $zero_64, 1
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; PIC: }
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; PIC: bb.4.tail:
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; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
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; PIC: $v0_64 = DADDiu $zero_64, 0
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; PIC: }
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bb.0 (%ir-block.0):
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $a0_64
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BGEZ64 killed renamable $a0_64, %bb.2, implicit-def $at
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bb.1.iftrue:
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INLINEASM &".space 131068", 1
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$v0_64 = DADDiu $zero_64, 1
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PseudoReturn64 undef $ra_64, implicit killed $v0_64
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|
bb.2.tail:
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$v0_64 = DADDiu $zero_64, 0
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PseudoReturn64 undef $ra_64, implicit killed $v0_64
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|
|
...
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---
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|
|
|
name: expand_BGTZ64
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alignment: 8
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exposesReturnsTwice: false
|
|
legalized: false
|
|
regBankSelected: false
|
|
selected: false
|
|
failedISel: false
|
|
tracksRegLiveness: true
|
|
registers:
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|
liveins:
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|
- { reg: '$a0_64', virtual-reg: '' }
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|
frameInfo:
|
|
isFrameAddressTaken: false
|
|
isReturnAddressTaken: false
|
|
hasStackMap: false
|
|
hasPatchPoint: false
|
|
stackSize: 0
|
|
offsetAdjustment: 0
|
|
maxAlignment: 1
|
|
adjustsStack: false
|
|
hasCalls: false
|
|
stackProtector: ''
|
|
maxCallFrameSize: 0
|
|
hasOpaqueSPAdjustment: false
|
|
hasVAStart: false
|
|
hasMustTailInVarArgFunc: false
|
|
localFrameSize: 0
|
|
savePoint: []
|
|
restorePoint: []
|
|
fixedStack:
|
|
stack:
|
|
constants:
|
|
body: |
|
|
; MIPS64-LABEL: name: expand_BGTZ64
|
|
; MIPS64: bb.0 (%ir-block.0):
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; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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|
; MIPS64: BLEZ64 $a0_64, %bb.2, implicit-def $at {
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; MIPS64: $zero = SLL $zero, 0
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; MIPS64: }
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; MIPS64: bb.1 (%ir-block.0):
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; MIPS64: successors: %bb.3(0x80000000)
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; MIPS64: J %bb.3, implicit-def $at {
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; MIPS64: $zero = SLL $zero, 0
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; MIPS64: }
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; MIPS64: bb.2.iftrue:
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; MIPS64: INLINEASM &".space 131068", 1
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; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
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; MIPS64: $v0_64 = DADDiu $zero_64, 1
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; MIPS64: }
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; MIPS64: bb.3.tail:
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; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
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; MIPS64: $v0_64 = DADDiu $zero_64, 0
|
|
; MIPS64: }
|
|
; PIC-LABEL: name: expand_BGTZ64
|
|
; PIC: bb.0 (%ir-block.0):
|
|
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
|
; PIC: BLEZ64 $a0_64, %bb.3, implicit-def $at {
|
|
; PIC: $zero = SLL $zero, 0
|
|
; PIC: }
|
|
; PIC: bb.1 (%ir-block.0):
|
|
; PIC: successors: %bb.2(0x80000000)
|
|
; PIC: $sp_64 = DADDiu $sp_64, -16
|
|
; PIC: SD $ra_64, $sp_64, 0
|
|
; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
|
|
; PIC: $at_64 = DSLL $at_64, 16
|
|
; PIC: BAL_BR %bb.2, implicit-def $ra {
|
|
; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
|
|
; PIC: }
|
|
; PIC: bb.2 (%ir-block.0):
|
|
; PIC: successors: %bb.4(0x80000000)
|
|
; PIC: $at_64 = DADDu $ra_64, $at_64
|
|
; PIC: $ra_64 = LD $sp_64, 0
|
|
; PIC: JR64 $at_64 {
|
|
; PIC: $sp_64 = DADDiu $sp_64, 16
|
|
; PIC: }
|
|
; PIC: bb.3.iftrue:
|
|
; PIC: INLINEASM &".space 131068", 1
|
|
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
|
; PIC: $v0_64 = DADDiu $zero_64, 1
|
|
; PIC: }
|
|
; PIC: bb.4.tail:
|
|
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
|
; PIC: $v0_64 = DADDiu $zero_64, 0
|
|
; PIC: }
|
|
bb.0 (%ir-block.0):
|
|
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
|
liveins: $a0_64
|
|
|
|
BGTZ64 killed renamable $a0_64, %bb.2, implicit-def $at
|
|
|
|
bb.1.iftrue:
|
|
INLINEASM &".space 131068", 1
|
|
$v0_64 = DADDiu $zero_64, 1
|
|
PseudoReturn64 undef $ra_64, implicit killed $v0_64
|
|
|
|
bb.2.tail:
|
|
$v0_64 = DADDiu $zero_64, 0
|
|
PseudoReturn64 undef $ra_64, implicit killed $v0_64
|
|
|
|
...
|
|
---
|
|
|
|
name: expand_BLEZ64
|
|
alignment: 8
|
|
exposesReturnsTwice: false
|
|
legalized: false
|
|
regBankSelected: false
|
|
selected: false
|
|
failedISel: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
liveins:
|
|
- { reg: '$a0_64', virtual-reg: '' }
|
|
frameInfo:
|
|
isFrameAddressTaken: false
|
|
isReturnAddressTaken: false
|
|
hasStackMap: false
|
|
hasPatchPoint: false
|
|
stackSize: 0
|
|
offsetAdjustment: 0
|
|
maxAlignment: 1
|
|
adjustsStack: false
|
|
hasCalls: false
|
|
stackProtector: ''
|
|
maxCallFrameSize: 0
|
|
hasOpaqueSPAdjustment: false
|
|
hasVAStart: false
|
|
hasMustTailInVarArgFunc: false
|
|
localFrameSize: 0
|
|
savePoint: []
|
|
restorePoint: []
|
|
fixedStack:
|
|
stack:
|
|
constants:
|
|
body: |
|
|
; MIPS64-LABEL: name: expand_BLEZ64
|
|
; MIPS64: bb.0 (%ir-block.0):
|
|
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
|
; MIPS64: BGTZ64 $a0_64, %bb.2, implicit-def $at {
|
|
; MIPS64: $zero = SLL $zero, 0
|
|
; MIPS64: }
|
|
; MIPS64: bb.1 (%ir-block.0):
|
|
; MIPS64: successors: %bb.3(0x80000000)
|
|
; MIPS64: J %bb.3, implicit-def $at {
|
|
; MIPS64: $zero = SLL $zero, 0
|
|
; MIPS64: }
|
|
; MIPS64: bb.2.iftrue:
|
|
; MIPS64: INLINEASM &".space 131068", 1
|
|
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
|
; MIPS64: $v0_64 = DADDiu $zero_64, 1
|
|
; MIPS64: }
|
|
; MIPS64: bb.3.tail:
|
|
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
|
; MIPS64: $v0_64 = DADDiu $zero_64, 0
|
|
; MIPS64: }
|
|
; PIC-LABEL: name: expand_BLEZ64
|
|
; PIC: bb.0 (%ir-block.0):
|
|
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
|
; PIC: BGTZ64 $a0_64, %bb.3, implicit-def $at {
|
|
; PIC: $zero = SLL $zero, 0
|
|
; PIC: }
|
|
; PIC: bb.1 (%ir-block.0):
|
|
; PIC: successors: %bb.2(0x80000000)
|
|
; PIC: $sp_64 = DADDiu $sp_64, -16
|
|
; PIC: SD $ra_64, $sp_64, 0
|
|
; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
|
|
; PIC: $at_64 = DSLL $at_64, 16
|
|
; PIC: BAL_BR %bb.2, implicit-def $ra {
|
|
; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
|
|
; PIC: }
|
|
; PIC: bb.2 (%ir-block.0):
|
|
; PIC: successors: %bb.4(0x80000000)
|
|
; PIC: $at_64 = DADDu $ra_64, $at_64
|
|
; PIC: $ra_64 = LD $sp_64, 0
|
|
; PIC: JR64 $at_64 {
|
|
; PIC: $sp_64 = DADDiu $sp_64, 16
|
|
; PIC: }
|
|
; PIC: bb.3.iftrue:
|
|
; PIC: INLINEASM &".space 131068", 1
|
|
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
|
; PIC: $v0_64 = DADDiu $zero_64, 1
|
|
; PIC: }
|
|
; PIC: bb.4.tail:
|
|
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
|
; PIC: $v0_64 = DADDiu $zero_64, 0
|
|
; PIC: }
|
|
bb.0 (%ir-block.0):
|
|
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
|
liveins: $a0_64
|
|
|
|
BLEZ64 killed renamable $a0_64, %bb.2, implicit-def $at
|
|
|
|
bb.1.iftrue:
|
|
INLINEASM &".space 131068", 1
|
|
$v0_64 = DADDiu $zero_64, 1
|
|
PseudoReturn64 undef $ra_64, implicit killed $v0_64
|
|
|
|
bb.2.tail:
|
|
$v0_64 = DADDiu $zero_64, 0
|
|
PseudoReturn64 undef $ra_64, implicit killed $v0_64
|
|
|
|
...
|
|
---
|
|
|
|
name: expand_BLTZ64
|
|
alignment: 8
|
|
exposesReturnsTwice: false
|
|
legalized: false
|
|
regBankSelected: false
|
|
selected: false
|
|
failedISel: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
liveins:
|
|
- { reg: '$a0_64', virtual-reg: '' }
|
|
frameInfo:
|
|
isFrameAddressTaken: false
|
|
isReturnAddressTaken: false
|
|
hasStackMap: false
|
|
hasPatchPoint: false
|
|
stackSize: 0
|
|
offsetAdjustment: 0
|
|
maxAlignment: 1
|
|
adjustsStack: false
|
|
hasCalls: false
|
|
stackProtector: ''
|
|
maxCallFrameSize: 0
|
|
hasOpaqueSPAdjustment: false
|
|
hasVAStart: false
|
|
hasMustTailInVarArgFunc: false
|
|
localFrameSize: 0
|
|
savePoint: []
|
|
restorePoint: []
|
|
fixedStack:
|
|
stack:
|
|
constants:
|
|
body: |
|
|
; MIPS64-LABEL: name: expand_BLTZ64
|
|
; MIPS64: bb.0 (%ir-block.0):
|
|
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
|
; MIPS64: BGEZ64 $a0_64, %bb.2, implicit-def $at {
|
|
; MIPS64: $zero = SLL $zero, 0
|
|
; MIPS64: }
|
|
; MIPS64: bb.1 (%ir-block.0):
|
|
; MIPS64: successors: %bb.3(0x80000000)
|
|
; MIPS64: J %bb.3, implicit-def $at {
|
|
; MIPS64: $zero = SLL $zero, 0
|
|
; MIPS64: }
|
|
; MIPS64: bb.2.iftrue:
|
|
; MIPS64: INLINEASM &".space 131068", 1
|
|
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
|
; MIPS64: $v0_64 = DADDiu $zero_64, 1
|
|
; MIPS64: }
|
|
; MIPS64: bb.3.tail:
|
|
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
|
; MIPS64: $v0_64 = DADDiu $zero_64, 0
|
|
; MIPS64: }
|
|
; PIC-LABEL: name: expand_BLTZ64
|
|
; PIC: bb.0 (%ir-block.0):
|
|
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
|
|
; PIC: BGEZ64 $a0_64, %bb.3, implicit-def $at {
|
|
; PIC: $zero = SLL $zero, 0
|
|
; PIC: }
|
|
; PIC: bb.1 (%ir-block.0):
|
|
; PIC: successors: %bb.2(0x80000000)
|
|
; PIC: $sp_64 = DADDiu $sp_64, -16
|
|
; PIC: SD $ra_64, $sp_64, 0
|
|
; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
|
|
; PIC: $at_64 = DSLL $at_64, 16
|
|
; PIC: BAL_BR %bb.2, implicit-def $ra {
|
|
; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
|
|
; PIC: }
|
|
; PIC: bb.2 (%ir-block.0):
|
|
; PIC: successors: %bb.4(0x80000000)
|
|
; PIC: $at_64 = DADDu $ra_64, $at_64
|
|
; PIC: $ra_64 = LD $sp_64, 0
|
|
; PIC: JR64 $at_64 {
|
|
; PIC: $sp_64 = DADDiu $sp_64, 16
|
|
; PIC: }
|
|
; PIC: bb.3.iftrue:
|
|
; PIC: INLINEASM &".space 131068", 1
|
|
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
|
; PIC: $v0_64 = DADDiu $zero_64, 1
|
|
; PIC: }
|
|
; PIC: bb.4.tail:
|
|
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
|
|
; PIC: $v0_64 = DADDiu $zero_64, 0
|
|
; PIC: }
|
|
bb.0 (%ir-block.0):
|
|
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
|
liveins: $a0_64
|
|
|
|
BLTZ64 killed renamable $a0_64, %bb.2, implicit-def $at
|
|
|
|
bb.1.iftrue:
|
|
INLINEASM &".space 131068", 1
|
|
$v0_64 = DADDiu $zero_64, 1
|
|
PseudoReturn64 undef $ra_64, implicit killed $v0_64
|
|
|
|
bb.2.tail:
|
|
$v0_64 = DADDiu $zero_64, 0
|
|
PseudoReturn64 undef $ra_64, implicit killed $v0_64
|
|
|
|
...
|