369891b674
In most cases, the type information attached to load and store instructions is meaningless and inconsistently applied. We can usually use ".b" loads and avoid the complexity of trying to assign the correct type. The one expectation is sign-extending load, which will continue to use ".s" to ensure the sign extension into a larger register is done correctly.
32 lines
1.2 KiB
LLVM
32 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
|
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_20 | FileCheck %s
|
|
; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_20 | %ptxas-verify %}
|
|
|
|
target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
|
|
target triple = "nvptx64-nvidia-cuda"
|
|
|
|
define void @_Z3foobbbPb(i1 zeroext %p1, i1 zeroext %p2, i1 zeroext %p3, ptr nocapture %output) {
|
|
; CHECK-LABEL: _Z3foobbbPb(
|
|
; CHECK: {
|
|
; CHECK-NEXT: .reg .pred %p<2>;
|
|
; CHECK-NEXT: .reg .b16 %rs<7>;
|
|
; CHECK-NEXT: .reg .b64 %rd<2>;
|
|
; CHECK-EMPTY:
|
|
; CHECK-NEXT: // %bb.0: // %entry
|
|
; CHECK-NEXT: ld.param.b8 %rs1, [_Z3foobbbPb_param_0];
|
|
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
|
|
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
|
|
; CHECK-NEXT: ld.param.b8 %rs3, [_Z3foobbbPb_param_1];
|
|
; CHECK-NEXT: ld.param.b8 %rs4, [_Z3foobbbPb_param_2];
|
|
; CHECK-NEXT: selp.b16 %rs5, %rs3, %rs4, %p1;
|
|
; CHECK-NEXT: and.b16 %rs6, %rs5, 1;
|
|
; CHECK-NEXT: ld.param.b64 %rd1, [_Z3foobbbPb_param_3];
|
|
; CHECK-NEXT: st.b8 [%rd1], %rs6;
|
|
; CHECK-NEXT: ret;
|
|
entry:
|
|
%.sink.v = select i1 %p1, i1 %p2, i1 %p3
|
|
%frombool5 = zext i1 %.sink.v to i8
|
|
store i8 %frombool5, ptr %output, align 1
|
|
ret void
|
|
}
|