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llvm-project/llvm/test/CodeGen/NVPTX/compare-int.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=nvptx -mcpu=sm_20 | FileCheck %s
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_20 | FileCheck %s
; RUN: %if ptxas && !ptxas-12.0 %{ llc < %s -mtriple=nvptx -mcpu=sm_20 | %ptxas-verify %}
; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_20 | %ptxas-verify %}
;; These tests should run for all targets
;;===-- Basic instruction selection tests ---------------------------------===;;
;;; i64
define i64 @icmp_eq_i64(i64 %a, i64 %b) {
; CHECK-LABEL: icmp_eq_i64(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b64 %rd<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b64 %rd1, [icmp_eq_i64_param_0];
; CHECK-NEXT: ld.param.b64 %rd2, [icmp_eq_i64_param_1];
; CHECK-NEXT: setp.eq.b64 %p1, %rd1, %rd2;
; CHECK-NEXT: selp.b64 %rd3, 1, 0, %p1;
; CHECK-NEXT: st.param.b64 [func_retval0], %rd3;
; CHECK-NEXT: ret;
%cmp = icmp eq i64 %a, %b
%ret = zext i1 %cmp to i64
ret i64 %ret
}
define i64 @icmp_ne_i64(i64 %a, i64 %b) {
; CHECK-LABEL: icmp_ne_i64(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b64 %rd<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b64 %rd1, [icmp_ne_i64_param_0];
; CHECK-NEXT: ld.param.b64 %rd2, [icmp_ne_i64_param_1];
; CHECK-NEXT: setp.ne.b64 %p1, %rd1, %rd2;
; CHECK-NEXT: selp.b64 %rd3, 1, 0, %p1;
; CHECK-NEXT: st.param.b64 [func_retval0], %rd3;
; CHECK-NEXT: ret;
%cmp = icmp ne i64 %a, %b
%ret = zext i1 %cmp to i64
ret i64 %ret
}
define i64 @icmp_ugt_i64(i64 %a, i64 %b) {
; CHECK-LABEL: icmp_ugt_i64(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b64 %rd<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b64 %rd1, [icmp_ugt_i64_param_0];
; CHECK-NEXT: ld.param.b64 %rd2, [icmp_ugt_i64_param_1];
; CHECK-NEXT: setp.gt.u64 %p1, %rd1, %rd2;
; CHECK-NEXT: selp.b64 %rd3, 1, 0, %p1;
; CHECK-NEXT: st.param.b64 [func_retval0], %rd3;
; CHECK-NEXT: ret;
%cmp = icmp ugt i64 %a, %b
%ret = zext i1 %cmp to i64
ret i64 %ret
}
define i64 @icmp_uge_i64(i64 %a, i64 %b) {
; CHECK-LABEL: icmp_uge_i64(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b64 %rd<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b64 %rd1, [icmp_uge_i64_param_0];
; CHECK-NEXT: ld.param.b64 %rd2, [icmp_uge_i64_param_1];
; CHECK-NEXT: setp.ge.u64 %p1, %rd1, %rd2;
; CHECK-NEXT: selp.b64 %rd3, 1, 0, %p1;
; CHECK-NEXT: st.param.b64 [func_retval0], %rd3;
; CHECK-NEXT: ret;
%cmp = icmp uge i64 %a, %b
%ret = zext i1 %cmp to i64
ret i64 %ret
}
define i64 @icmp_ult_i64(i64 %a, i64 %b) {
; CHECK-LABEL: icmp_ult_i64(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b64 %rd<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b64 %rd1, [icmp_ult_i64_param_0];
; CHECK-NEXT: ld.param.b64 %rd2, [icmp_ult_i64_param_1];
; CHECK-NEXT: setp.lt.u64 %p1, %rd1, %rd2;
; CHECK-NEXT: selp.b64 %rd3, 1, 0, %p1;
; CHECK-NEXT: st.param.b64 [func_retval0], %rd3;
; CHECK-NEXT: ret;
%cmp = icmp ult i64 %a, %b
%ret = zext i1 %cmp to i64
ret i64 %ret
}
define i64 @icmp_ule_i64(i64 %a, i64 %b) {
; CHECK-LABEL: icmp_ule_i64(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b64 %rd<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b64 %rd1, [icmp_ule_i64_param_0];
; CHECK-NEXT: ld.param.b64 %rd2, [icmp_ule_i64_param_1];
; CHECK-NEXT: setp.le.u64 %p1, %rd1, %rd2;
; CHECK-NEXT: selp.b64 %rd3, 1, 0, %p1;
; CHECK-NEXT: st.param.b64 [func_retval0], %rd3;
; CHECK-NEXT: ret;
%cmp = icmp ule i64 %a, %b
%ret = zext i1 %cmp to i64
ret i64 %ret
}
define i64 @icmp_sgt_i64(i64 %a, i64 %b) {
; CHECK-LABEL: icmp_sgt_i64(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b64 %rd<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b64 %rd1, [icmp_sgt_i64_param_0];
; CHECK-NEXT: ld.param.b64 %rd2, [icmp_sgt_i64_param_1];
; CHECK-NEXT: setp.gt.s64 %p1, %rd1, %rd2;
; CHECK-NEXT: selp.b64 %rd3, 1, 0, %p1;
; CHECK-NEXT: st.param.b64 [func_retval0], %rd3;
; CHECK-NEXT: ret;
%cmp = icmp sgt i64 %a, %b
%ret = zext i1 %cmp to i64
ret i64 %ret
}
define i64 @icmp_sge_i64(i64 %a, i64 %b) {
; CHECK-LABEL: icmp_sge_i64(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b64 %rd<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b64 %rd1, [icmp_sge_i64_param_0];
; CHECK-NEXT: ld.param.b64 %rd2, [icmp_sge_i64_param_1];
; CHECK-NEXT: setp.ge.s64 %p1, %rd1, %rd2;
; CHECK-NEXT: selp.b64 %rd3, 1, 0, %p1;
; CHECK-NEXT: st.param.b64 [func_retval0], %rd3;
; CHECK-NEXT: ret;
%cmp = icmp sge i64 %a, %b
%ret = zext i1 %cmp to i64
ret i64 %ret
}
define i64 @icmp_slt_i64(i64 %a, i64 %b) {
; CHECK-LABEL: icmp_slt_i64(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b64 %rd<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b64 %rd1, [icmp_slt_i64_param_0];
; CHECK-NEXT: ld.param.b64 %rd2, [icmp_slt_i64_param_1];
; CHECK-NEXT: setp.lt.s64 %p1, %rd1, %rd2;
; CHECK-NEXT: selp.b64 %rd3, 1, 0, %p1;
; CHECK-NEXT: st.param.b64 [func_retval0], %rd3;
; CHECK-NEXT: ret;
%cmp = icmp slt i64 %a, %b
%ret = zext i1 %cmp to i64
ret i64 %ret
}
define i64 @icmp_sle_i64(i64 %a, i64 %b) {
; CHECK-LABEL: icmp_sle_i64(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b64 %rd<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b64 %rd1, [icmp_sle_i64_param_0];
; CHECK-NEXT: ld.param.b64 %rd2, [icmp_sle_i64_param_1];
; CHECK-NEXT: setp.le.s64 %p1, %rd1, %rd2;
; CHECK-NEXT: selp.b64 %rd3, 1, 0, %p1;
; CHECK-NEXT: st.param.b64 [func_retval0], %rd3;
; CHECK-NEXT: ret;
%cmp = icmp sle i64 %a, %b
%ret = zext i1 %cmp to i64
ret i64 %ret
}
;;; i32
define i32 @icmp_eq_i32(i32 %a, i32 %b) {
; CHECK-LABEL: icmp_eq_i32(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b32 %r1, [icmp_eq_i32_param_0];
; CHECK-NEXT: ld.param.b32 %r2, [icmp_eq_i32_param_1];
; CHECK-NEXT: setp.eq.b32 %p1, %r1, %r2;
; CHECK-NEXT: selp.b32 %r3, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%cmp = icmp eq i32 %a, %b
%ret = zext i1 %cmp to i32
ret i32 %ret
}
define i32 @icmp_ne_i32(i32 %a, i32 %b) {
; CHECK-LABEL: icmp_ne_i32(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b32 %r1, [icmp_ne_i32_param_0];
; CHECK-NEXT: ld.param.b32 %r2, [icmp_ne_i32_param_1];
; CHECK-NEXT: setp.ne.b32 %p1, %r1, %r2;
; CHECK-NEXT: selp.b32 %r3, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%cmp = icmp ne i32 %a, %b
%ret = zext i1 %cmp to i32
ret i32 %ret
}
define i32 @icmp_ugt_i32(i32 %a, i32 %b) {
; CHECK-LABEL: icmp_ugt_i32(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b32 %r1, [icmp_ugt_i32_param_0];
; CHECK-NEXT: ld.param.b32 %r2, [icmp_ugt_i32_param_1];
; CHECK-NEXT: setp.gt.u32 %p1, %r1, %r2;
; CHECK-NEXT: selp.b32 %r3, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%cmp = icmp ugt i32 %a, %b
%ret = zext i1 %cmp to i32
ret i32 %ret
}
define i32 @icmp_uge_i32(i32 %a, i32 %b) {
; CHECK-LABEL: icmp_uge_i32(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b32 %r1, [icmp_uge_i32_param_0];
; CHECK-NEXT: ld.param.b32 %r2, [icmp_uge_i32_param_1];
; CHECK-NEXT: setp.ge.u32 %p1, %r1, %r2;
; CHECK-NEXT: selp.b32 %r3, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%cmp = icmp uge i32 %a, %b
%ret = zext i1 %cmp to i32
ret i32 %ret
}
define i32 @icmp_ult_i32(i32 %a, i32 %b) {
; CHECK-LABEL: icmp_ult_i32(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b32 %r1, [icmp_ult_i32_param_0];
; CHECK-NEXT: ld.param.b32 %r2, [icmp_ult_i32_param_1];
; CHECK-NEXT: setp.lt.u32 %p1, %r1, %r2;
; CHECK-NEXT: selp.b32 %r3, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%cmp = icmp ult i32 %a, %b
%ret = zext i1 %cmp to i32
ret i32 %ret
}
define i32 @icmp_ule_i32(i32 %a, i32 %b) {
; CHECK-LABEL: icmp_ule_i32(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b32 %r1, [icmp_ule_i32_param_0];
; CHECK-NEXT: ld.param.b32 %r2, [icmp_ule_i32_param_1];
; CHECK-NEXT: setp.le.u32 %p1, %r1, %r2;
; CHECK-NEXT: selp.b32 %r3, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%cmp = icmp ule i32 %a, %b
%ret = zext i1 %cmp to i32
ret i32 %ret
}
define i32 @icmp_sgt_i32(i32 %a, i32 %b) {
; CHECK-LABEL: icmp_sgt_i32(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b32 %r1, [icmp_sgt_i32_param_0];
; CHECK-NEXT: ld.param.b32 %r2, [icmp_sgt_i32_param_1];
; CHECK-NEXT: setp.gt.s32 %p1, %r1, %r2;
; CHECK-NEXT: selp.b32 %r3, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%cmp = icmp sgt i32 %a, %b
%ret = zext i1 %cmp to i32
ret i32 %ret
}
define i32 @icmp_sge_i32(i32 %a, i32 %b) {
; CHECK-LABEL: icmp_sge_i32(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b32 %r1, [icmp_sge_i32_param_0];
; CHECK-NEXT: ld.param.b32 %r2, [icmp_sge_i32_param_1];
; CHECK-NEXT: setp.ge.s32 %p1, %r1, %r2;
; CHECK-NEXT: selp.b32 %r3, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%cmp = icmp sge i32 %a, %b
%ret = zext i1 %cmp to i32
ret i32 %ret
}
define i32 @icmp_slt_i32(i32 %a, i32 %b) {
; CHECK-LABEL: icmp_slt_i32(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b32 %r1, [icmp_slt_i32_param_0];
; CHECK-NEXT: ld.param.b32 %r2, [icmp_slt_i32_param_1];
; CHECK-NEXT: setp.lt.s32 %p1, %r1, %r2;
; CHECK-NEXT: selp.b32 %r3, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%cmp = icmp slt i32 %a, %b
%ret = zext i1 %cmp to i32
ret i32 %ret
}
define i32 @icmp_sle_i32(i32 %a, i32 %b) {
; CHECK-LABEL: icmp_sle_i32(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b32 %r1, [icmp_sle_i32_param_0];
; CHECK-NEXT: ld.param.b32 %r2, [icmp_sle_i32_param_1];
; CHECK-NEXT: setp.le.s32 %p1, %r1, %r2;
; CHECK-NEXT: selp.b32 %r3, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%cmp = icmp sle i32 %a, %b
%ret = zext i1 %cmp to i32
ret i32 %ret
}
;;; i16
define i16 @icmp_eq_i16(i16 %a, i16 %b) {
; CHECK-LABEL: icmp_eq_i16(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b16 %rs<3>;
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b16 %rs1, [icmp_eq_i16_param_0];
; CHECK-NEXT: ld.param.b16 %rs2, [icmp_eq_i16_param_1];
; CHECK-NEXT: setp.eq.b16 %p1, %rs1, %rs2;
; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%cmp = icmp eq i16 %a, %b
%ret = zext i1 %cmp to i16
ret i16 %ret
}
define i16 @icmp_ne_i16(i16 %a, i16 %b) {
; CHECK-LABEL: icmp_ne_i16(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b16 %rs<3>;
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b16 %rs1, [icmp_ne_i16_param_0];
; CHECK-NEXT: ld.param.b16 %rs2, [icmp_ne_i16_param_1];
; CHECK-NEXT: setp.ne.b16 %p1, %rs1, %rs2;
; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%cmp = icmp ne i16 %a, %b
%ret = zext i1 %cmp to i16
ret i16 %ret
}
define i16 @icmp_ugt_i16(i16 %a, i16 %b) {
; CHECK-LABEL: icmp_ugt_i16(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b16 %rs<3>;
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b16 %rs1, [icmp_ugt_i16_param_0];
; CHECK-NEXT: ld.param.b16 %rs2, [icmp_ugt_i16_param_1];
; CHECK-NEXT: setp.gt.u16 %p1, %rs1, %rs2;
; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%cmp = icmp ugt i16 %a, %b
%ret = zext i1 %cmp to i16
ret i16 %ret
}
define i16 @icmp_uge_i16(i16 %a, i16 %b) {
; CHECK-LABEL: icmp_uge_i16(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b16 %rs<3>;
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b16 %rs1, [icmp_uge_i16_param_0];
; CHECK-NEXT: ld.param.b16 %rs2, [icmp_uge_i16_param_1];
; CHECK-NEXT: setp.ge.u16 %p1, %rs1, %rs2;
; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%cmp = icmp uge i16 %a, %b
%ret = zext i1 %cmp to i16
ret i16 %ret
}
define i16 @icmp_ult_i16(i16 %a, i16 %b) {
; CHECK-LABEL: icmp_ult_i16(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b16 %rs<3>;
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b16 %rs1, [icmp_ult_i16_param_0];
; CHECK-NEXT: ld.param.b16 %rs2, [icmp_ult_i16_param_1];
; CHECK-NEXT: setp.lt.u16 %p1, %rs1, %rs2;
; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%cmp = icmp ult i16 %a, %b
%ret = zext i1 %cmp to i16
ret i16 %ret
}
define i16 @icmp_ule_i16(i16 %a, i16 %b) {
; CHECK-LABEL: icmp_ule_i16(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b16 %rs<3>;
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b16 %rs1, [icmp_ule_i16_param_0];
; CHECK-NEXT: ld.param.b16 %rs2, [icmp_ule_i16_param_1];
; CHECK-NEXT: setp.le.u16 %p1, %rs1, %rs2;
; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%cmp = icmp ule i16 %a, %b
%ret = zext i1 %cmp to i16
ret i16 %ret
}
define i16 @icmp_sgt_i16(i16 %a, i16 %b) {
; CHECK-LABEL: icmp_sgt_i16(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b16 %rs<3>;
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b16 %rs1, [icmp_sgt_i16_param_0];
; CHECK-NEXT: ld.param.b16 %rs2, [icmp_sgt_i16_param_1];
; CHECK-NEXT: setp.gt.s16 %p1, %rs1, %rs2;
; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%cmp = icmp sgt i16 %a, %b
%ret = zext i1 %cmp to i16
ret i16 %ret
}
define i16 @icmp_sge_i16(i16 %a, i16 %b) {
; CHECK-LABEL: icmp_sge_i16(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b16 %rs<3>;
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b16 %rs1, [icmp_sge_i16_param_0];
; CHECK-NEXT: ld.param.b16 %rs2, [icmp_sge_i16_param_1];
; CHECK-NEXT: setp.ge.s16 %p1, %rs1, %rs2;
; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%cmp = icmp sge i16 %a, %b
%ret = zext i1 %cmp to i16
ret i16 %ret
}
define i16 @icmp_slt_i16(i16 %a, i16 %b) {
; CHECK-LABEL: icmp_slt_i16(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b16 %rs<3>;
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b16 %rs1, [icmp_slt_i16_param_0];
; CHECK-NEXT: ld.param.b16 %rs2, [icmp_slt_i16_param_1];
; CHECK-NEXT: setp.lt.s16 %p1, %rs1, %rs2;
; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%cmp = icmp slt i16 %a, %b
%ret = zext i1 %cmp to i16
ret i16 %ret
}
define i16 @icmp_sle_i16(i16 %a, i16 %b) {
; CHECK-LABEL: icmp_sle_i16(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b16 %rs<3>;
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b16 %rs1, [icmp_sle_i16_param_0];
; CHECK-NEXT: ld.param.b16 %rs2, [icmp_sle_i16_param_1];
; CHECK-NEXT: setp.le.s16 %p1, %rs1, %rs2;
; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%cmp = icmp sle i16 %a, %b
%ret = zext i1 %cmp to i16
ret i16 %ret
}
;;; i8
define i8 @icmp_eq_i8(i8 %a, i8 %b) {
; Comparison happens in 16-bit
; CHECK-LABEL: icmp_eq_i8(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b16 %rs<3>;
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b8 %rs1, [icmp_eq_i8_param_0];
; CHECK-NEXT: ld.param.b8 %rs2, [icmp_eq_i8_param_1];
; CHECK-NEXT: setp.eq.b16 %p1, %rs1, %rs2;
; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%cmp = icmp eq i8 %a, %b
%ret = zext i1 %cmp to i8
ret i8 %ret
}
define i8 @icmp_ne_i8(i8 %a, i8 %b) {
; Comparison happens in 16-bit
; CHECK-LABEL: icmp_ne_i8(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b16 %rs<3>;
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b8 %rs1, [icmp_ne_i8_param_0];
; CHECK-NEXT: ld.param.b8 %rs2, [icmp_ne_i8_param_1];
; CHECK-NEXT: setp.ne.b16 %p1, %rs1, %rs2;
; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%cmp = icmp ne i8 %a, %b
%ret = zext i1 %cmp to i8
ret i8 %ret
}
define i8 @icmp_ugt_i8(i8 %a, i8 %b) {
; Comparison happens in 16-bit
; CHECK-LABEL: icmp_ugt_i8(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b16 %rs<3>;
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b8 %rs1, [icmp_ugt_i8_param_0];
; CHECK-NEXT: ld.param.b8 %rs2, [icmp_ugt_i8_param_1];
; CHECK-NEXT: setp.gt.u16 %p1, %rs1, %rs2;
; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%cmp = icmp ugt i8 %a, %b
%ret = zext i1 %cmp to i8
ret i8 %ret
}
define i8 @icmp_uge_i8(i8 %a, i8 %b) {
; Comparison happens in 16-bit
; CHECK-LABEL: icmp_uge_i8(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b16 %rs<3>;
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b8 %rs1, [icmp_uge_i8_param_0];
; CHECK-NEXT: ld.param.b8 %rs2, [icmp_uge_i8_param_1];
; CHECK-NEXT: setp.ge.u16 %p1, %rs1, %rs2;
; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%cmp = icmp uge i8 %a, %b
%ret = zext i1 %cmp to i8
ret i8 %ret
}
define i8 @icmp_ult_i8(i8 %a, i8 %b) {
; Comparison happens in 16-bit
; CHECK-LABEL: icmp_ult_i8(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b16 %rs<3>;
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b8 %rs1, [icmp_ult_i8_param_0];
; CHECK-NEXT: ld.param.b8 %rs2, [icmp_ult_i8_param_1];
; CHECK-NEXT: setp.lt.u16 %p1, %rs1, %rs2;
; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%cmp = icmp ult i8 %a, %b
%ret = zext i1 %cmp to i8
ret i8 %ret
}
define i8 @icmp_ule_i8(i8 %a, i8 %b) {
; Comparison happens in 16-bit
; CHECK-LABEL: icmp_ule_i8(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b16 %rs<3>;
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b8 %rs1, [icmp_ule_i8_param_0];
; CHECK-NEXT: ld.param.b8 %rs2, [icmp_ule_i8_param_1];
; CHECK-NEXT: setp.le.u16 %p1, %rs1, %rs2;
; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%cmp = icmp ule i8 %a, %b
%ret = zext i1 %cmp to i8
ret i8 %ret
}
define i8 @icmp_sgt_i8(i8 %a, i8 %b) {
; Comparison happens in 16-bit
; CHECK-LABEL: icmp_sgt_i8(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b16 %rs<3>;
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.s8 %rs1, [icmp_sgt_i8_param_0];
; CHECK-NEXT: ld.param.s8 %rs2, [icmp_sgt_i8_param_1];
; CHECK-NEXT: setp.gt.s16 %p1, %rs1, %rs2;
; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%cmp = icmp sgt i8 %a, %b
%ret = zext i1 %cmp to i8
ret i8 %ret
}
define i8 @icmp_sge_i8(i8 %a, i8 %b) {
; Comparison happens in 16-bit
; CHECK-LABEL: icmp_sge_i8(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b16 %rs<3>;
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.s8 %rs1, [icmp_sge_i8_param_0];
; CHECK-NEXT: ld.param.s8 %rs2, [icmp_sge_i8_param_1];
; CHECK-NEXT: setp.ge.s16 %p1, %rs1, %rs2;
; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%cmp = icmp sge i8 %a, %b
%ret = zext i1 %cmp to i8
ret i8 %ret
}
define i8 @icmp_slt_i8(i8 %a, i8 %b) {
; Comparison happens in 16-bit
; CHECK-LABEL: icmp_slt_i8(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b16 %rs<3>;
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.s8 %rs1, [icmp_slt_i8_param_0];
; CHECK-NEXT: ld.param.s8 %rs2, [icmp_slt_i8_param_1];
; CHECK-NEXT: setp.lt.s16 %p1, %rs1, %rs2;
; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%cmp = icmp slt i8 %a, %b
%ret = zext i1 %cmp to i8
ret i8 %ret
}
define i8 @icmp_sle_i8(i8 %a, i8 %b) {
; Comparison happens in 16-bit
; CHECK-LABEL: icmp_sle_i8(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
; CHECK-NEXT: .reg .b16 %rs<3>;
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.s8 %rs1, [icmp_sle_i8_param_0];
; CHECK-NEXT: ld.param.s8 %rs2, [icmp_sle_i8_param_1];
; CHECK-NEXT: setp.le.s16 %p1, %rs1, %rs2;
; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%cmp = icmp sle i8 %a, %b
%ret = zext i1 %cmp to i8
ret i8 %ret
}
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