369891b674
In most cases, the type information attached to load and store instructions is meaningless and inconsistently applied. We can usually use ".b" loads and avoid the complexity of trying to assign the correct type. The one expectation is sign-extending load, which will continue to use ".s" to ensure the sign extension into a larger register is done correctly.
38 lines
1.6 KiB
LLVM
38 lines
1.6 KiB
LLVM
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_30 -mattr=+ptx60 | FileCheck %s
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; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_30 -mattr=+ptx60 | %ptxas-verify %}
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declare i32 @llvm.nvvm.fns(i32, i32, i32)
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; CHECK-LABEL: .func{{.*}}fns
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define i32 @fns(i32 %mask, i32 %base, i32 %offset) {
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; CHECK: ld.param.b32 [[MASK:%r[0-9]+]], [fns_param_0];
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; CHECK: ld.param.b32 [[BASE:%r[0-9]+]], [fns_param_1];
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; CHECK: ld.param.b32 [[OFFSET:%r[0-9]+]], [fns_param_2];
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; CHECK: fns.b32 {{%r[0-9]+}}, [[MASK]], [[BASE]], [[OFFSET]];
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%r0 = call i32 @llvm.nvvm.fns(i32 %mask, i32 %base, i32 %offset);
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; CHECK: fns.b32 {{%r[0-9]+}}, [[MASK]], [[BASE]], 0;
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%r1 = call i32 @llvm.nvvm.fns(i32 %mask, i32 %base, i32 0);
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%r01 = add i32 %r0, %r1;
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; CHECK: fns.b32 {{%r[0-9]+}}, [[MASK]], 1, [[OFFSET]];
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%r2 = call i32 @llvm.nvvm.fns(i32 %mask, i32 1, i32 %offset);
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; CHECK: fns.b32 {{%r[0-9]+}}, [[MASK]], 1, 0;
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%r3 = call i32 @llvm.nvvm.fns(i32 %mask, i32 1, i32 0);
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%r23 = add i32 %r2, %r3;
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%r0123 = add i32 %r01, %r23;
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; CHECK: fns.b32 {{%r[0-9]+}}, 2, [[BASE]], [[OFFSET]];
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%r4 = call i32 @llvm.nvvm.fns(i32 2, i32 %base, i32 %offset);
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; CHECK: fns.b32 {{%r[0-9]+}}, 2, [[BASE]], 0;
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%r5 = call i32 @llvm.nvvm.fns(i32 2, i32 %base, i32 0);
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%r45 = add i32 %r4, %r5;
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; CHECK: fns.b32 {{%r[0-9]+}}, 2, 1, [[OFFSET]];
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%r6 = call i32 @llvm.nvvm.fns(i32 2, i32 1, i32 %offset);
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; CHECK: fns.b32 {{%r[0-9]+}}, 2, 1, 0;
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%r7 = call i32 @llvm.nvvm.fns(i32 2, i32 1, i32 0);
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%r67 = add i32 %r6, %r7;
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%r4567 = add i32 %r45, %r67;
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%r = add i32 %r0123, %r4567;
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ret i32 %r;
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}
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