76c9bfefa4
These classes are redundant, as the untyped "Int" classes can be used for all float operations. This change is intended to be as minimal as possible and leaves the many potential simplifications and refactors this exposes as future work.
132 lines
4.9 KiB
LLVM
132 lines
4.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_100a -mattr=+ptx86 | FileCheck %s
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; RUN: %if ptxas-12.8 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_100a -mattr=+ptx86 | %ptxas-verify -arch=sm_100a %}
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declare float @llvm.nvvm.redux.sync.fmin(float, i32)
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define float @redux_sync_fmin(float %src, i32 %mask) {
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; CHECK-LABEL: redux_sync_fmin(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<4>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [redux_sync_fmin_param_0];
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; CHECK-NEXT: ld.param.b32 %r2, [redux_sync_fmin_param_1];
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; CHECK-NEXT: redux.sync.min.f32 %r3, %r1, %r2;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
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; CHECK-NEXT: ret;
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%val = call float @llvm.nvvm.redux.sync.fmin(float %src, i32 %mask)
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ret float %val
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}
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declare float @llvm.nvvm.redux.sync.fmin.abs(float, i32)
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define float @redux_sync_fmin_abs(float %src, i32 %mask) {
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; CHECK-LABEL: redux_sync_fmin_abs(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<4>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [redux_sync_fmin_abs_param_0];
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; CHECK-NEXT: ld.param.b32 %r2, [redux_sync_fmin_abs_param_1];
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; CHECK-NEXT: redux.sync.min.abs.f32 %r3, %r1, %r2;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
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; CHECK-NEXT: ret;
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%val = call float @llvm.nvvm.redux.sync.fmin.abs(float %src, i32 %mask)
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ret float %val
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}
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declare float @llvm.nvvm.redux.sync.fmin.NaN(float, i32)
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define float @redux_sync_fmin_NaN(float %src, i32 %mask) {
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; CHECK-LABEL: redux_sync_fmin_NaN(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<4>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [redux_sync_fmin_NaN_param_0];
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; CHECK-NEXT: ld.param.b32 %r2, [redux_sync_fmin_NaN_param_1];
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; CHECK-NEXT: redux.sync.min.NaN.f32 %r3, %r1, %r2;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
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; CHECK-NEXT: ret;
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%val = call float @llvm.nvvm.redux.sync.fmin.NaN(float %src, i32 %mask)
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ret float %val
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}
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declare float @llvm.nvvm.redux.sync.fmin.abs.NaN(float, i32)
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define float @redux_sync_fmin_abs_NaN(float %src, i32 %mask) {
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; CHECK-LABEL: redux_sync_fmin_abs_NaN(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<4>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [redux_sync_fmin_abs_NaN_param_0];
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; CHECK-NEXT: ld.param.b32 %r2, [redux_sync_fmin_abs_NaN_param_1];
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; CHECK-NEXT: redux.sync.min.abs.NaN.f32 %r3, %r1, %r2;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
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; CHECK-NEXT: ret;
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%val = call float @llvm.nvvm.redux.sync.fmin.abs.NaN(float %src, i32 %mask)
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ret float %val
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}
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declare float @llvm.nvvm.redux.sync.fmax(float, i32)
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define float @redux_sync_fmax(float %src, i32 %mask) {
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; CHECK-LABEL: redux_sync_fmax(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<4>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [redux_sync_fmax_param_0];
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; CHECK-NEXT: ld.param.b32 %r2, [redux_sync_fmax_param_1];
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; CHECK-NEXT: redux.sync.max.f32 %r3, %r1, %r2;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
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; CHECK-NEXT: ret;
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%val = call float @llvm.nvvm.redux.sync.fmax(float %src, i32 %mask)
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ret float %val
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}
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declare float @llvm.nvvm.redux.sync.fmax.abs(float, i32)
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define float @redux_sync_fmax_abs(float %src, i32 %mask) {
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; CHECK-LABEL: redux_sync_fmax_abs(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<4>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [redux_sync_fmax_abs_param_0];
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; CHECK-NEXT: ld.param.b32 %r2, [redux_sync_fmax_abs_param_1];
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; CHECK-NEXT: redux.sync.max.abs.f32 %r3, %r1, %r2;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
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; CHECK-NEXT: ret;
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%val = call float @llvm.nvvm.redux.sync.fmax.abs(float %src, i32 %mask)
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ret float %val
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}
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declare float @llvm.nvvm.redux.sync.fmax.NaN(float, i32)
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define float @redux_sync_fmax_NaN(float %src, i32 %mask) {
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; CHECK-LABEL: redux_sync_fmax_NaN(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<4>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [redux_sync_fmax_NaN_param_0];
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; CHECK-NEXT: ld.param.b32 %r2, [redux_sync_fmax_NaN_param_1];
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; CHECK-NEXT: redux.sync.max.NaN.f32 %r3, %r1, %r2;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
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; CHECK-NEXT: ret;
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%val = call float @llvm.nvvm.redux.sync.fmax.NaN(float %src, i32 %mask)
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ret float %val
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}
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declare float @llvm.nvvm.redux.sync.fmax.abs.NaN(float, i32)
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define float @redux_sync_fmax_abs_NaN(float %src, i32 %mask) {
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; CHECK-LABEL: redux_sync_fmax_abs_NaN(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<4>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [redux_sync_fmax_abs_NaN_param_0];
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; CHECK-NEXT: ld.param.b32 %r2, [redux_sync_fmax_abs_NaN_param_1];
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; CHECK-NEXT: redux.sync.max.abs.NaN.f32 %r3, %r1, %r2;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
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; CHECK-NEXT: ret;
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%val = call float @llvm.nvvm.redux.sync.fmax.abs.NaN(float %src, i32 %mask)
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ret float %val
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}
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