369891b674
In most cases, the type information attached to load and store instructions is meaningless and inconsistently applied. We can usually use ".b" loads and avoid the complexity of trying to assign the correct type. The one expectation is sign-extending load, which will continue to use ".s" to ensure the sign extension into a larger register is done correctly.
43 lines
1.5 KiB
LLVM
43 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_35 | FileCheck %s
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; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 | %ptxas-verify %}
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declare i64 @llvm.nvvm.rotate.b64(i64, i32)
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declare i64 @llvm.nvvm.rotate.right.b64(i64, i32)
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define i64 @rotate64(i64 %a, i32 %b) {
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; CHECK-LABEL: rotate64(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<5>;
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; CHECK-NEXT: .reg .b64 %rd<3>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b64 %rd1, [rotate64_param_0];
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; CHECK-NEXT: mov.b64 {%r1, %r2}, %rd1;
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; CHECK-NEXT: shf.l.wrap.b32 %r3, %r1, %r2, 3;
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; CHECK-NEXT: shf.l.wrap.b32 %r4, %r2, %r1, 3;
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; CHECK-NEXT: mov.b64 %rd2, {%r4, %r3};
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; CHECK-NEXT: st.param.b64 [func_retval0], %rd2;
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; CHECK-NEXT: ret;
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%val = tail call i64 @llvm.nvvm.rotate.b64(i64 %a, i32 3)
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ret i64 %val
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}
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define i64 @rotateright64(i64 %a, i32 %b) {
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; CHECK-LABEL: rotateright64(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<5>;
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; CHECK-NEXT: .reg .b64 %rd<3>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b64 %rd1, [rotateright64_param_0];
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; CHECK-NEXT: mov.b64 {%r1, %r2}, %rd1;
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; CHECK-NEXT: shf.r.wrap.b32 %r3, %r2, %r1, 3;
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; CHECK-NEXT: shf.r.wrap.b32 %r4, %r1, %r2, 3;
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; CHECK-NEXT: mov.b64 %rd2, {%r4, %r3};
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; CHECK-NEXT: st.param.b64 [func_retval0], %rd2;
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; CHECK-NEXT: ret;
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%val = tail call i64 @llvm.nvvm.rotate.right.b64(i64 %a, i32 3)
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ret i64 %val
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}
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