3508f12335
This patch adds the initial support for vector functions and register banks within GlobalISel. With this patch, we are able to support simple functions that return vectors, and also functions that perform simple operations. This patch also: - Legalizes vector types for G_AND, G_OR, G_XOR, G_ADD, G_SUB, G_BITCAST, G_FADD, G_FSUB - Introduce initial support for bitcasting (that will need to be extended upon) - Add various different test cases to for test vector support within GlobalISel Differential Revision: https://reviews.llvm.org/D137785
126 lines
3.2 KiB
LLVM
126 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel -o - \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
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define float @float_add(float %a, float %b) {
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; CHECK-LABEL: float_add:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xsaddsp f1, f1, f2
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; CHECK-NEXT: blr
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entry:
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%add = fadd float %a, %b
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ret float %add
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}
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define double @double_add(double %a, double %b) {
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; CHECK-LABEL: double_add:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xsadddp f1, f1, f2
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; CHECK-NEXT: blr
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entry:
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%add = fadd double %a, %b
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ret double %add
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}
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define float @float_sub(float %a, float %b) {
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; CHECK-LABEL: float_sub:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xssubsp f1, f1, f2
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; CHECK-NEXT: blr
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entry:
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%sub = fsub float %a, %b
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ret float %sub
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}
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define float @float_mul(float %a, float %b) {
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; CHECK-LABEL: float_mul:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xsmulsp f1, f1, f2
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; CHECK-NEXT: blr
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entry:
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%mul = fmul float %a, %b
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ret float %mul
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}
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define float @float_div(float %a, float %b) {
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; CHECK-LABEL: float_div:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xsdivsp f1, f1, f2
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; CHECK-NEXT: blr
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entry:
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%div = fdiv float %a, %b
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ret float %div
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}
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define <4 x float> @test_fadd_v4f32(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test_fadd_v4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvaddsp v2, v2, v3
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; CHECK-NEXT: blr
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%res = fadd <4 x float> %a, %b
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ret <4 x float> %res
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}
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define <2 x double> @test_fadd_v2f64(<2 x double> %a, <2 x double> %b) {
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; CHECK-LABEL: test_fadd_v2f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvadddp v2, v2, v3
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; CHECK-NEXT: blr
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%res = fadd <2 x double> %a, %b
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ret <2 x double> %res
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}
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define <4 x float> @test_fsub_v4f32(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test_fsub_v4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvsubsp v2, v2, v3
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; CHECK-NEXT: blr
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%res = fsub <4 x float> %a, %b
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ret <4 x float> %res
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}
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define <2 x double> @test_fsub_v2f64(<2 x double> %a, <2 x double> %b) {
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; CHECK-LABEL: test_fsub_v2f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvsubdp v2, v2, v3
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; CHECK-NEXT: blr
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%res = fsub <2 x double> %a, %b
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ret <2 x double> %res
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}
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define <4 x float> @test_fmul_v4f32(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test_fmul_v4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvmulsp v2, v2, v3
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; CHECK-NEXT: blr
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%res = fmul <4 x float> %a, %b
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ret <4 x float> %res
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}
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define <2 x double> @test_fmul_v2f64(<2 x double> %a, <2 x double> %b) {
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; CHECK-LABEL: test_fmul_v2f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvmuldp v2, v2, v3
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; CHECK-NEXT: blr
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%res = fmul <2 x double> %a, %b
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ret <2 x double> %res
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}
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define <4 x float> @test_fdiv_v4f32(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test_fdiv_v4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvdivsp v2, v2, v3
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; CHECK-NEXT: blr
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%res = fdiv <4 x float> %a, %b
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ret <4 x float> %res
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}
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define <2 x double> @test_fdiv_v2f64(<2 x double> %a, <2 x double> %b) {
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; CHECK-LABEL: test_fdiv_v2f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvdivdp v2, v2, v3
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; CHECK-NEXT: blr
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%res = fdiv <2 x double> %a, %b
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ret <2 x double> %res
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}
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