3508f12335
This patch adds the initial support for vector functions and register banks within GlobalISel. With this patch, we are able to support simple functions that return vectors, and also functions that perform simple operations. This patch also: - Legalizes vector types for G_AND, G_OR, G_XOR, G_ADD, G_SUB, G_BITCAST, G_FADD, G_FSUB - Introduce initial support for bitcasting (that will need to be extended upon) - Add various different test cases to for test vector support within GlobalISel Differential Revision: https://reviews.llvm.org/D137785
175 lines
4.4 KiB
LLVM
175 lines
4.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -global-isel -o - < %s | FileCheck %s
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -mattr=-vsx -global-isel -o - < %s | \
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; RUN: FileCheck %s --check-prefix=NO-VSX
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define <16 x i8> @test_and_v16i8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: test_and_v16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xxland v2, v2, v3
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; CHECK-NEXT: blr
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;
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; NO-VSX-LABEL: test_and_v16i8:
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; NO-VSX: # %bb.0:
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; NO-VSX-NEXT: vand v2, v2, v3
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; NO-VSX-NEXT: blr
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%res = and <16 x i8> %a, %b
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ret <16 x i8> %res
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}
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define <16 x i8> @test_or_v16i8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: test_or_v16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xxlor v2, v2, v3
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; CHECK-NEXT: blr
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;
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; NO-VSX-LABEL: test_or_v16i8:
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; NO-VSX: # %bb.0:
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; NO-VSX-NEXT: vor v2, v2, v3
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; NO-VSX-NEXT: blr
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%res = or <16 x i8> %a, %b
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ret <16 x i8> %res
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}
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define <16 x i8> @test_xor_v16i8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: test_xor_v16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xxlxor v2, v2, v3
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; CHECK-NEXT: blr
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;
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; NO-VSX-LABEL: test_xor_v16i8:
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; NO-VSX: # %bb.0:
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; NO-VSX-NEXT: vxor v2, v2, v3
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; NO-VSX-NEXT: blr
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%res = xor <16 x i8> %a, %b
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ret <16 x i8> %res
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}
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define <8 x i16> @test_and_v8i16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test_and_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xxland v2, v2, v3
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; CHECK-NEXT: blr
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;
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; NO-VSX-LABEL: test_and_v8i16:
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; NO-VSX: # %bb.0:
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; NO-VSX-NEXT: vand v2, v2, v3
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; NO-VSX-NEXT: blr
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%res = and <8 x i16> %a, %b
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ret <8 x i16> %res
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}
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define <8 x i16> @test_or_v8i16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test_or_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xxlor v2, v2, v3
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; CHECK-NEXT: blr
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;
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; NO-VSX-LABEL: test_or_v8i16:
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; NO-VSX: # %bb.0:
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; NO-VSX-NEXT: vor v2, v2, v3
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; NO-VSX-NEXT: blr
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%res = or <8 x i16> %a, %b
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ret <8 x i16> %res
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}
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define <8 x i16> @test_xor_v8i16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test_xor_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xxlxor v2, v2, v3
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; CHECK-NEXT: blr
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;
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; NO-VSX-LABEL: test_xor_v8i16:
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; NO-VSX: # %bb.0:
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; NO-VSX-NEXT: vxor v2, v2, v3
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; NO-VSX-NEXT: blr
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%res = xor <8 x i16> %a, %b
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ret <8 x i16> %res
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}
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define <4 x i32> @test_and_v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_and_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xxland v2, v2, v3
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; CHECK-NEXT: blr
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;
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; NO-VSX-LABEL: test_and_v4i32:
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; NO-VSX: # %bb.0:
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; NO-VSX-NEXT: vand v2, v2, v3
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; NO-VSX-NEXT: blr
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%res = and <4 x i32> %a, %b
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ret <4 x i32> %res
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}
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define <4 x i32> @test_or_v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_or_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xxlor v2, v2, v3
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; CHECK-NEXT: blr
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;
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; NO-VSX-LABEL: test_or_v4i32:
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; NO-VSX: # %bb.0:
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; NO-VSX-NEXT: vor v2, v2, v3
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; NO-VSX-NEXT: blr
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%res = or <4 x i32> %a, %b
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ret <4 x i32> %res
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}
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define <4 x i32> @test_xor_v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_xor_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xxlxor v2, v2, v3
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; CHECK-NEXT: blr
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;
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; NO-VSX-LABEL: test_xor_v4i32:
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; NO-VSX: # %bb.0:
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; NO-VSX-NEXT: vxor v2, v2, v3
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; NO-VSX-NEXT: blr
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%res = xor <4 x i32> %a, %b
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ret <4 x i32> %res
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}
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define <2 x i64> @test_and_v2i64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_and_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xxland v2, v2, v3
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; CHECK-NEXT: blr
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;
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; NO-VSX-LABEL: test_and_v2i64:
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; NO-VSX: # %bb.0:
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; NO-VSX-NEXT: vand v2, v2, v3
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; NO-VSX-NEXT: blr
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%res = and <2 x i64> %a, %b
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ret <2 x i64> %res
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}
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define <2 x i64> @test_or_v2i64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_or_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xxlor v2, v2, v3
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; CHECK-NEXT: blr
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;
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; NO-VSX-LABEL: test_or_v2i64:
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; NO-VSX: # %bb.0:
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; NO-VSX-NEXT: vor v2, v2, v3
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; NO-VSX-NEXT: blr
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%res = or <2 x i64> %a, %b
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ret <2 x i64> %res
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}
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define <2 x i64> @test_xor_v2i64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_xor_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xxlxor v2, v2, v3
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; CHECK-NEXT: blr
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;
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; NO-VSX-LABEL: test_xor_v2i64:
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; NO-VSX: # %bb.0:
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; NO-VSX-NEXT: vxor v2, v2, v3
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; NO-VSX-NEXT: blr
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%res = xor <2 x i64> %a, %b
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ret <2 x i64> %res
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}
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