2d80505401
Exploit the per global code model attribute on AIX. On AIX we need to update both the code sequence used to access the global (either 1 or 2 instructions for small and large code model respectively) and the storage mapping class that we emit the toc entry. --------- Co-authored-by: Amy Kwan <akwan0907@gmail.com>
167 lines
5.3 KiB
LLVM
167 lines
5.3 KiB
LLVM
; RUN: llc --verify-machineinstrs -mtriple powerpc-ibm-aix --code-model=small < \
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; RUN: %s | FileCheck --check-prefixes=CHECK,CHECK32,CHECK-SMALL,CHECK-SMALL32 %s
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; RUN: llc --verify-machineinstrs -mtriple powerpc-ibm-aix --code-model=large < \
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; RUN: %s | FileCheck --check-prefixes=CHECK,CHECK32,CHECK-LARGE,CHECK-LARGE32 %s
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; RUN: llc --verify-machineinstrs -mtriple powerpc64-ibm-aix --code-model=small < \
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; RUN: %s | FileCheck --check-prefixes=CHECK,CHECK64,CHECK-SMALL,CHECK-SMALL64 %s
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; RUN: llc --verify-machineinstrs -mtriple powerpc64-ibm-aix --code-model=large < \
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; RUN: %s | FileCheck --check-prefixes=CHECK,CHECK64,CHECK-LARGE,CHECK-LARGE64 %s
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@a = external dso_local global i32, code_model "small", align 4
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@b = external dso_local global i32, code_model "large", align 4
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@c = dso_local global i32 55, code_model "small", align 4
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@d = dso_local global i32 41, code_model "large", align 4
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@e = external dso_local global i32, align 4
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@f = dso_local global i32 2748, align 4
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@large_aliasee = global i32 10, code_model "large", align 4
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@small_aliasee = global i32 171, code_model "small", align 4
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@normal_aliasee = global i32 2748, align 4
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@al = alias i32, ptr @large_aliasee
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@as = alias i32, ptr @small_aliasee
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@an = alias i32, ptr @normal_aliasee
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define i32 @A() local_unnamed_addr {
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entry:
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%0 = load i32, ptr @a, align 4
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ret i32 %0
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}
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; CHECK32: lwz [[SCRATCH:[0-9]+]], L..C[[TL_A:[0-9]+]](2) # @a
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; CHECK64: ld [[SCRATCH:[0-9]+]], L..C[[TL_A:[0-9]+]](2) # @a
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; CHECK: lwz 3, 0([[SCRATCH]])
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; CHECK: blr
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define i32 @B() local_unnamed_addr {
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entry:
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%0 = load i32, ptr @b, align 4
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ret i32 %0
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}
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; CHECK: addis [[HI:[0-9]+]], L..C[[TL_B:[0-9]+]]@u(2)
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; CHECK32: lwz [[ADDR:[0-9]+]], L..C[[TL_B]]@l([[HI]])
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; CHECK64: ld [[ADDR:[0-9]+]], L..C[[TL_B]]@l([[HI]])
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; CHECK: lwz 3, 0([[ADDR]])
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; CHECK: blr
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define i32 @C() local_unnamed_addr {
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entry:
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%0 = load i32, ptr @c, align 4
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ret i32 %0
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}
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; CHECK32: lwz [[SCRATCH:[0-9]+]], L..C[[TL_C:[0-9]+]](2) # @c
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; CHECK64: ld [[SCRATCH:[0-9]+]], L..C[[TL_C:[0-9]+]](2) # @c
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; CHECK: lwz 3, 0([[SCRATCH]])
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; CHECK: blr
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define i32 @D() local_unnamed_addr {
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entry:
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%0 = load i32, ptr @d, align 4
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ret i32 %0
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}
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; CHECK: addis [[HI:[0-9]+]], L..C[[TL_D:[0-9]+]]@u(2)
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; CHECK32: lwz [[ADDR:[0-9]+]], L..C[[TL_D]]@l([[HI]])
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; CHECK64: ld [[ADDR:[0-9]+]], L..C[[TL_D]]@l([[HI]])
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; CHECK: lwz 3, 0([[ADDR]])
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; CHECK: blr
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define i32 @E() {
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entry:
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%0 = load i32, ptr @e, align 4
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ret i32 %0
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}
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; CHECK-LARGE: addis [[HI:[0-9]+]], L..C[[TL_E:[0-9]+]]@u(2)
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; CHECK-LARGE32: lwz [[SCRATCH:[0-9]+]], L..C[[TL_E]]@l([[HI]])
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; CHECK-SMALL32: lwz [[SCRATCH:[0-9]+]], L..C[[TL_E:[0-9]+]](2)
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; CHECK-LARGE64: ld [[SCRATCH:[0-9]+]], L..C[[TL_E]]@l([[HI]])
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; CHECK-SMALL64: ld [[SCRATCH:[0-9]+]], L..C[[TL_E:[0-9]+]](2)
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; CHECK: lwz 3, 0([[SCRATCH]])
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; CHECK: blr
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define i32 @F() {
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entry:
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%0 = load i32, ptr @f, align 4
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ret i32 %0
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}
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; CHECK-LARGE: addis [[HI:[0-9]+]], L..C[[TL_F:[0-9]+]]@u(2)
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; CHECK-LARGE32: lwz [[SCRATCH:[0-9]+]], L..C[[TL_F]]@l([[HI]])
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; CHECK-SMALL32: lwz [[SCRATCH:[0-9]+]], L..C[[TL_F:[0-9]+]](2)
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; CHECK-LARGE64: ld [[SCRATCH:[0-9]+]], L..C[[TL_F]]@l([[HI]])
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; CHECK-SMALL64: ld [[SCRATCH:[0-9]+]], L..C[[TL_F:[0-9]+]](2)
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; CHECK: lwz 3, 0([[SCRATCH]])
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; CHECK: blr
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define noundef nonnull ptr @addr_a() local_unnamed_addr {
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entry:
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ret ptr @a
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}
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; CHECK32: lwz 3, L..C[[TL_A]](2) # @a
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; CHECK64: ld 3, L..C[[TL_A]](2) # @a
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; CHECK: blr
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define noundef nonnull ptr @addr_b() local_unnamed_addr {
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entry:
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ret ptr @b
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}
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; CHECK: addis [[HI:[0-9]+]], L..C[[TL_B]]@u(2)
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; CHECK32: lwz 3, L..C[[TL_B]]@l([[HI]])
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; CHECK64: ld 3, L..C[[TL_B]]@l([[HI]])
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; CHECK: blr
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define noundef nonnull ptr @addr_c() local_unnamed_addr {
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entry:
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ret ptr @c
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}
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; CHECK32: lwz 3, L..C[[TL_C]](2) # @c
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; CHECK64: ld 3, L..C[[TL_C]](2) # @c
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; CHECK: blr
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define noundef nonnull ptr @addr_d() local_unnamed_addr {
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entry:
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ret ptr @d
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}
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; CHECK: addis [[HI:[0-9]+]], L..C[[TL_D]]@u(2)
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; CHECK32: lwz 3, L..C[[TL_D]]@l([[HI]])
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; CHECK64: ld 3, L..C[[TL_D]]@l([[HI]])
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; CHECK: blr
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define i32 @G() {
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%tmp = load i32, ptr @al
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ret i32 %tmp
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}
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; CHECK: addis [[HI:[0-9]+]], L..C[[TL_AL:[0-9]+]]@u(2)
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; CHECK32: lwz [[ADDR:[0-9]+]], L..C[[TL_AL]]@l([[HI]])
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; CHECK64: ld [[ADDR:[0-9]+]], L..C[[TL_AL]]@l([[HI]])
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; CHECK: lwz 3, 0([[ADDR]])
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define i32 @H() {
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%tmp = load i32, ptr @as
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ret i32 %tmp
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}
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; CHECK32: lwz [[ADDR:[0-9]+]], L..C[[TL_AS:[0-9]+]](2)
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; CHECK64: ld [[ADDR:[0-9]+]], L..C[[TL_AS:[0-9]+]](2)
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; CHECK: lwz 3, 0([[ADDR]])
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;; Check TOC entires have correct storage mapping class
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; CHECK: L..C[[TL_A]]:
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; CHECK: .tc a[TC],a[UA]
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; CHECK: L..C[[TL_B]]:
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; CHECK: .tc b[TE],b[UA]
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; CHECK: L..C[[TL_C]]:
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; CHECK: .tc c[TC],c[RW]
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; CHECK: L..C[[TL_D]]:
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; CHECK: .tc d[TE],d[RW]
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; CHECK: L..C[[TL_E]]:
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; CHECK-SMALL: .tc e[TC],e[UA]
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; CHECK-LARGE: .tc e[TE],e[UA]
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; CHECK: L..C[[TL_F]]:
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; CHECK-SMALL: .tc f[TC],f[RW]
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; CHECK-LARGE: .tc f[TE],f[RW]
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; CHECK: L..C[[TL_AL]]:
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; CHECK: .tc al[TE],al
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; CHECK: L..C[[TL_AS]]:
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; CHECK: .tc as[TC],as
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