427fb35192
The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, amyk, nikic, PowerPC Differential Revision: https://reviews.llvm.org/D135470
86 lines
2.0 KiB
LLVM
86 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -verify-machineinstrs -mtriple powerpc64le -mcpu=pwr9 | FileCheck %s
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; RUN: llc < %s -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 | FileCheck %s
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; RUN: opt < %s -passes="default<O3>" -S -mtriple powerpc64le -mcpu=pwr9 | FileCheck %s --check-prefix=OPT
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define i64 @raw() {
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; CHECK-LABEL: raw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: darn 3, 2
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; CHECK-NEXT: blr
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entry:
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%0 = call i64 @llvm.ppc.darnraw()
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ret i64 %0
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}
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define i64 @conditioned() {
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; CHECK-LABEL: conditioned:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: darn 3, 1
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; CHECK-NEXT: blr
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entry:
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%0 = call i64 @llvm.ppc.darn()
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ret i64 %0
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}
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define signext i32 @word() {
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; CHECK-LABEL: word:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: darn 3, 0
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; CHECK-NEXT: extsw 3, 3
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; CHECK-NEXT: blr
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entry:
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%0 = call i32 @llvm.ppc.darn32()
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ret i32 %0
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}
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define i64 @darn_side_effect() {
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; CHECK-LABEL: darn_side_effect:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: darn 3, 2
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; CHECK-NEXT: darn 3, 1
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; CHECK-NEXT: blr
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; OPT-LABEL: @darn_side_effect
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; OPT: call i64 @llvm.ppc.darnraw()
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; OPT-NEXT: call i64 @llvm.ppc.darn()
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entry:
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%0 = call i64 @llvm.ppc.darnraw()
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%1 = call i64 @llvm.ppc.darn()
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ret i64 %1
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}
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define void @darn_loop(ptr noundef %darn) {
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; OPT-LABEL: @darn_loop
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; OPT-COUNT-32: tail call i64 @llvm.ppc.darn()
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entry:
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%inc = alloca i32, align 4
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store i32 0, ptr %inc, align 4
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br label %cond
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cond:
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%0 = load i32, ptr %inc, align 4
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%cmp = icmp ne i32 %0, 32
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br i1 %cmp, label %body, label %end_loop
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body:
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%1 = call i64 @llvm.ppc.darn()
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%2 = load i32, ptr %inc, align 4
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%idx = getelementptr inbounds i64, ptr %darn, i32 %2
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store i64 %1, ptr %idx, align 8
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br label %incr
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incr:
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%3 = load i32, ptr %inc, align 4
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%ninc = add nsw i32 %3, 1
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store i32 %ninc, ptr %inc, align 4
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br label %cond
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end_loop:
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ret void
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}
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declare i64 @llvm.ppc.darn()
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declare i64 @llvm.ppc.darnraw()
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declare i32 @llvm.ppc.darn32()
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