c65b4d64d4
Alignment of an alloca in IR can be lower than the preferred alignment on purpose, but this override essentially treats the preferred alignment as the minimum alignment. The patch changes this behavior to always use the specified alignment. If alignment is not set explicitly in LLVM IR, it is set to DL.getPrefTypeAlign(Ty) in computeAllocaDefaultAlign. Tests are changed as well: explicit alignment is increased to match the preferred alignment if it changes output, or omitted when it is hard to determine the right value (e.g. for pointers, some structs, or weird types). Differential Revision: https://reviews.llvm.org/D135462
42 lines
1.2 KiB
LLVM
42 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-n32:64-S128-v256:256:256-v512:512:512"
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target triple = "powerpc64le-unknown-linux-gnu"
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%struct = type { [4 x i32], [20 x i8] }
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declare dso_local i32 @foo1(ptr byval(%struct) %var)
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declare dso_local void @foo(ptr %var)
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; check that 36bytes byval parameter is passed all in registers.
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define dso_local i32 @bar() {
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; CHECK-LABEL: bar:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: stdu 1, -80(1)
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; CHECK-NEXT: std 0, 96(1)
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; CHECK-NEXT: .cfi_def_cfa_offset 80
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: addi 3, 1, 40
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; CHECK-NEXT: bl foo
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; CHECK-NEXT: nop
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; CHECK-NEXT: lwz 7, 72(1)
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; CHECK-NEXT: ld 6, 64(1)
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; CHECK-NEXT: ld 5, 56(1)
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; CHECK-NEXT: ld 4, 48(1)
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; CHECK-NEXT: ld 3, 40(1)
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; CHECK-NEXT: bl foo1
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi 1, 1, 80
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; CHECK-NEXT: ld 0, 16(1)
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; CHECK-NEXT: mtlr 0
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; CHECK-NEXT: blr
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entry:
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%x = alloca %struct, align 8
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call void @foo(ptr %x)
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%r = call i32 @foo1(ptr byval(%struct) %x)
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ret i32 %r
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}
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