427fb35192
The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, amyk, nikic, PowerPC Differential Revision: https://reviews.llvm.org/D135470
448 lines
9.6 KiB
LLVM
448 lines
9.6 KiB
LLVM
; FIXME: FastISel currently returns false if it hits code that uses VSX
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; registers and with -fast-isel-abort=1 turned on the test case will then fail.
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; When fastisel better supports VSX fix up this test case.
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;
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s
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; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 -mattr=-vsx | FileCheck %s --check-prefix=PPC970
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; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=e500 -mattr=spe | FileCheck %s --check-prefix=SPE
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;; Tests for 970 don't use -fast-isel-abort=1 because we intentionally punt
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;; to SelectionDAG in some cases.
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; Test sitofp
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define void @sitofp_single_i64(i64 %a, float %b) nounwind {
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entry:
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; CHECK: sitofp_single_i64
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; PPC970: sitofp_single_i64
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%b.addr = alloca float, align 4
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%conv = sitofp i64 %a to float
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; CHECK: std
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; CHECK: lfd
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; CHECK: fcfids
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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; PPC970: frsp
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store float %conv, ptr %b.addr, align 4
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ret void
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}
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define void @sitofp_single_i32(i32 %a, float %b) nounwind {
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entry:
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; CHECK: sitofp_single_i32
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; PPC970: sitofp_single_i32
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%b.addr = alloca float, align 4
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%conv = sitofp i32 %a to float
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; CHECK: std
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; CHECK-NEXT: li
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; CHECK-NEXT: lfiwax
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; CHECK-NEXT: fcfids
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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; PPC970: frsp
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; SPE: efscfsi
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store float %conv, ptr %b.addr, align 4
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ret void
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}
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define void @sitofp_single_i16(i16 %a, float %b) nounwind {
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entry:
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; CHECK: sitofp_single_i16
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; PPC970: sitofp_single_i16
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%b.addr = alloca float, align 4
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%conv = sitofp i16 %a to float
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; CHECK: extsh
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; CHECK: std
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; CHECK: lfd
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; CHECK: fcfids
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; PPC970: extsh
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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; PPC970: frsp
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; SPE: extsh
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; SPE: efscfsi
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store float %conv, ptr %b.addr, align 4
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ret void
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}
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define void @sitofp_single_i8(i8 %a) nounwind {
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entry:
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; CHECK: sitofp_single_i8
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; PPC970: sitofp_single_i8
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%b.addr = alloca float, align 4
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%conv = sitofp i8 %a to float
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; CHECK: extsb
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; CHECK: std
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; CHECK: lfd
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; CHECK: fcfids
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; PPC970: extsb
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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; PPC970: frsp
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; SPE: extsb
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; SPE: efscfsi
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store float %conv, ptr %b.addr, align 4
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ret void
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}
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define void @sitofp_double_i32(i32 %a, double %b) nounwind {
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entry:
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; CHECK: sitofp_double_i32
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; PPC970: sitofp_double_i32
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%b.addr = alloca double, align 8
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%conv = sitofp i32 %a to double
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; CHECK: std
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; CHECK-NOT: ori
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; CHECK: li
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; CHECK-NOT: ori
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; CHECK: lfiwax
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; CHECK: fcfid
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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; SPE: efdcfsi
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store double %conv, ptr %b.addr, align 8
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ret void
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}
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define void @sitofp_double_i64(i64 %a, double %b) nounwind {
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entry:
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; CHECK: sitofp_double_i64
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; PPC970: sitofp_double_i64
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%b.addr = alloca double, align 8
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%conv = sitofp i64 %a to double
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; CHECK: std
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; CHECK: lfd
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; CHECK: fcfid
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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store double %conv, ptr %b.addr, align 8
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ret void
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}
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define void @sitofp_double_i16(i16 %a, double %b) nounwind {
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entry:
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; CHECK: sitofp_double_i16
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; PPC970: sitofp_double_i16
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%b.addr = alloca double, align 8
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%conv = sitofp i16 %a to double
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; CHECK: extsh
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; CHECK: std
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; CHECK: lfd
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; CHECK: fcfid
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; PPC970: extsh
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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; SPE: extsh
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; SPE: efdcfsi
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store double %conv, ptr %b.addr, align 8
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ret void
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}
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define void @sitofp_double_i8(i8 %a, double %b) nounwind {
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entry:
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; CHECK: sitofp_double_i8
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; PPC970: sitofp_double_i8
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%b.addr = alloca double, align 8
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%conv = sitofp i8 %a to double
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; CHECK: extsb
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; CHECK: std
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; CHECK: lfd
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; CHECK: fcfid
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; PPC970: extsb
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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; SPE: extsb
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; SPE: efdcfsi
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store double %conv, ptr %b.addr, align 8
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ret void
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}
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; Test uitofp
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define void @uitofp_single_i64(i64 %a, float %b) nounwind {
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entry:
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; CHECK: uitofp_single_i64
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; PPC970: uitofp_single_i64
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%b.addr = alloca float, align 4
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%conv = uitofp i64 %a to float
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; CHECK: std
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; CHECK: lfd
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; CHECK: fcfidus
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; PPC970-NOT: fcfidus
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store float %conv, ptr %b.addr, align 4
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ret void
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}
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define void @uitofp_single_i32(i32 %a, float %b) nounwind {
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entry:
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; CHECK: uitofp_single_i32
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; PPC970: uitofp_single_i32
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%b.addr = alloca float, align 4
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%conv = uitofp i32 %a to float
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; CHECK: std
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; CHECK-NOT: ori
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; CHECK: li
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; CHECK-NOT: ori
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; CHECK: lfiwzx
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; CHECK: fcfidus
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; PPC970-NOT: lfiwzx
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; PPC970-NOT: fcfidus
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; SPE: efscfui
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store float %conv, ptr %b.addr, align 4
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ret void
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}
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define void @uitofp_single_i16(i16 %a, float %b) nounwind {
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entry:
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; CHECK: uitofp_single_i16
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; PPC970: uitofp_single_i16
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%b.addr = alloca float, align 4
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%conv = uitofp i16 %a to float
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; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 48
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; CHECK: std
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; CHECK: lfd
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; CHECK: fcfidus
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; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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; PPC970: frsp
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; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
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; SPE: efscfui
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store float %conv, ptr %b.addr, align 4
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ret void
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}
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define void @uitofp_single_i8(i8 %a) nounwind {
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entry:
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; CHECK: uitofp_single_i8
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; PPC970: uitofp_single_i8
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%b.addr = alloca float, align 4
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%conv = uitofp i8 %a to float
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; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 56
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; CHECK: std
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; CHECK: lfd
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; CHECK: fcfidus
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; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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; PPC970: frsp
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; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
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; SPE: efscfui
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store float %conv, ptr %b.addr, align 4
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ret void
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}
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define void @uitofp_double_i64(i64 %a, double %b) nounwind {
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entry:
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; CHECK: uitofp_double_i64
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; PPC970: uitofp_double_i64
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%b.addr = alloca double, align 8
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%conv = uitofp i64 %a to double
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; CHECK: std
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; CHECK: lfd
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; CHECK: fcfidu
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; PPC970-NOT: fcfidu
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store double %conv, ptr %b.addr, align 8
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ret void
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}
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define void @uitofp_double_i32(i32 %a, double %b) nounwind {
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entry:
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; CHECK: uitofp_double_i32
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; PPC970: uitofp_double_i32
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%b.addr = alloca double, align 8
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%conv = uitofp i32 %a to double
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; CHECK: std
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; CHECK-NEXT: li
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; CHECK-NEXT: lfiwzx
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; CHECK-NEXT: fcfidu
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; PPC970-NOT: lfiwzx
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; PPC970-NOT: fcfidu
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; SPE: efdcfui
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store double %conv, ptr %b.addr, align 8
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ret void
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}
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define void @uitofp_double_i16(i16 %a, double %b) nounwind {
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entry:
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; CHECK: uitofp_double_i16
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; PPC970: uitofp_double_i16
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%b.addr = alloca double, align 8
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%conv = uitofp i16 %a to double
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; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 48
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; CHECK: std
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; CHECK: lfd
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; CHECK: fcfidu
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; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
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; SPE: efdcfui
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store double %conv, ptr %b.addr, align 8
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ret void
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}
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define void @uitofp_double_i8(i8 %a, double %b) nounwind {
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entry:
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; CHECK: uitofp_double_i8
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; PPC970: uitofp_double_i8
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%b.addr = alloca double, align 8
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%conv = uitofp i8 %a to double
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; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 56
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; CHECK: std
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; CHECK: lfd
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; CHECK: fcfidu
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; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
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; SPE: efdcfui
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store double %conv, ptr %b.addr, align 8
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ret void
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}
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; Test fptosi
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define void @fptosi_float_i32(float %a) nounwind {
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entry:
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; CHECK: fptosi_float_i32
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; PPC970: fptosi_float_i32
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%b.addr = alloca i32, align 4
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%conv = fptosi float %a to i32
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; CHECK: fctiwz
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; CHECK: stfd
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; CHECK: lwa
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; PPC970: fctiwz
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; PPC970: stfd
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; PPC970: lwa
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; SPE: efsctsi
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store i32 %conv, ptr %b.addr, align 4
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ret void
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}
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define void @fptosi_float_i64(float %a) nounwind {
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entry:
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; CHECK: fptosi_float_i64
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; PPC970: fptosi_float_i64
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%b.addr = alloca i64, align 4
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%conv = fptosi float %a to i64
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; CHECK: fctidz
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; CHECK: stfd
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; CHECK: ld
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; PPC970: fctidz
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; PPC970: stfd
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; PPC970: ld
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store i64 %conv, ptr %b.addr, align 4
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ret void
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}
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define void @fptosi_double_i32(double %a) nounwind {
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entry:
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; CHECK: fptosi_double_i32
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; PPC970: fptosi_double_i32
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%b.addr = alloca i32, align 8
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%conv = fptosi double %a to i32
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; CHECK: fctiwz
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; CHECK: stfd
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; CHECK: lwa
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; PPC970: fctiwz
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; PPC970: stfd
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; PPC970: lwa
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; SPE: efdctsi
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store i32 %conv, ptr %b.addr, align 8
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ret void
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}
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define void @fptosi_double_i64(double %a) nounwind {
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entry:
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; CHECK: fptosi_double_i64
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; PPC970: fptosi_double_i64
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%b.addr = alloca i64, align 8
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%conv = fptosi double %a to i64
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; CHECK: fctidz
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; CHECK: stfd
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; CHECK: ld
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; PPC970: fctidz
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; PPC970: stfd
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; PPC970: ld
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store i64 %conv, ptr %b.addr, align 8
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ret void
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}
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; Test fptoui
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define void @fptoui_float_i32(float %a) nounwind {
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entry:
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; CHECK: fptoui_float_i32
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; PPC970: fptoui_float_i32
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%b.addr = alloca i32, align 4
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%conv = fptoui float %a to i32
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; CHECK: fctiwuz
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; CHECK: stfd
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; CHECK: lwz
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; PPC970: fctidz
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; PPC970: stfd
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; PPC970: lwz
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; SPE: efsctui
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store i32 %conv, ptr %b.addr, align 4
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ret void
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}
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define void @fptoui_float_i64(float %a) nounwind {
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entry:
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; CHECK: fptoui_float_i64
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; PPC970: fptoui_float_i64
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%b.addr = alloca i64, align 4
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%conv = fptoui float %a to i64
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; CHECK: fctiduz
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; CHECK: stfd
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; CHECK: ld
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; PPC970-NOT: fctiduz
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store i64 %conv, ptr %b.addr, align 4
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ret void
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}
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define void @fptoui_double_i32(double %a) nounwind {
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entry:
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; CHECK: fptoui_double_i32
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; PPC970: fptoui_double_i32
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%b.addr = alloca i32, align 8
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%conv = fptoui double %a to i32
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; CHECK: fctiwuz
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; CHECK: stfd
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; CHECK: lwz
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; PPC970: fctidz
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; PPC970: stfd
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; PPC970: lwz
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; SPE: efdctui
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store i32 %conv, ptr %b.addr, align 8
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ret void
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}
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define void @fptoui_double_i64(double %a) nounwind {
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entry:
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; CHECK: fptoui_double_i64
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; PPC970: fptoui_double_i64
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%b.addr = alloca i64, align 8
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%conv = fptoui double %a to i64
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; CHECK: fctiduz
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; CHECK: stfd
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; CHECK: ld
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; PPC970-NOT: fctiduz
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store i64 %conv, ptr %b.addr, align 8
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ret void
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}
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