2534dc120a
This patch turns on support for CR bit accesses for Power8 and above. The reason why CR bits are turned on as the default for Power8 and above is that because later architectures make use of builtins and instructions that require CR bit accesses (such as the use of setbc in the vector string isolate predicate and bcd builtins on Power10). This patch also adds the clang portion to allow for turning on CR bits in the front end if the user so desires to. Differential Revision: https://reviews.llvm.org/D124060
188 lines
2.8 KiB
LLVM
188 lines
2.8 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu -fast-isel -O0 < %s | FileCheck %s
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define i1 @TestULT(double %t0) {
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; CHECK-LABEL: TestULT:
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; CHECK: fcmpu
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; CHECK: blr
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entry:
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%t1 = fcmp ult double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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define i1 @TestULE(double %t0) {
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; CHECK-LABEL: TestULE:
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; CHECK: xscmpudp
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; CHECK-NEXT: ble
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; CHECK: blr
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entry:
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%t1 = fcmp ule double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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define i1 @TestUNE(double %t0) {
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; CHECK-LABEL: TestUNE:
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; CHECK: xscmpudp
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; CHECK-NEXT: bne
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; CHECK: blr
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entry:
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%t1 = fcmp une double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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define i1 @TestUEQ(double %t0) {
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; CHECK-LABEL: TestUEQ:
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; CHECK: fcmpu
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; CHECK: blr
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entry:
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%t1 = fcmp ueq double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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define i1 @TestUGT(double %t0) {
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; CHECK-LABEL: TestUGT:
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; CHECK: fcmpu
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; CHECK: blr
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entry:
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%t1 = fcmp ugt double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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define i1 @TestUGE(double %t0) {
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; CHECK-LABEL: TestUGE:
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; CHECK: xscmpudp
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; CHECK-NEXT: bge
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; CHECK: blr
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entry:
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%t1 = fcmp uge double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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define i1 @TestOLT(double %t0) {
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; CHECK-LABEL: TestOLT:
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; CHECK: xscmpudp
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; CHECK-NEXT: blt
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; CHECK: blr
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entry:
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%t1 = fcmp olt double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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define i1 @TestOLE(double %t0) {
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; CHECK-LABEL: TestOLE:
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; CHECK: fcmpu
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; CHECK: blr
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entry:
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%t1 = fcmp ole double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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define i1 @TestONE(double %t0) {
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; CHECK-LABEL: TestONE:
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; CHECK: fcmpu
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; CHECK: blr
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entry:
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%t1 = fcmp one double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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define i1 @TestOEQ(double %t0) {
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; CHECK-LABEL: TestOEQ:
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; CHECK: xscmpudp
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; CHECK-NEXT: beq
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; CHECK: blr
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entry:
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%t1 = fcmp oeq double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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define i1 @TestOGT(double %t0) {
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; CHECK-LABEL: TestOGT:
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; CHECK: xscmpudp
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; CHECK-NEXT: bgt
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; CHECK: blr
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entry:
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%t1 = fcmp ogt double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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define i1 @TestOGE(double %t0) {
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; CHECK-LABEL: TestOGE:
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; CHECK: fcmpu
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; CHECK: blr
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entry:
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%t1 = fcmp oge double %t0, 0.000000e+00
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br i1 %t1, label %good, label %bad
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bad:
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ret i1 false
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good:
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ret i1 true
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}
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