b922a36211
PowerPC subtargets prior to Power9 use the 'legacy' itinerary way to provide scheduling information. This patch re-writes the tablegen file to define the scheduling information in the new SchedModel way, which can bring improvements to some benchmarks. Reviewed By: shchenz Differential Revision: https://reviews.llvm.org/D154488
45 lines
1.4 KiB
LLVM
45 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names < %s \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
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@res = dso_local local_unnamed_addr global i32 0, align 4
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@res2 = dso_local local_unnamed_addr global i32 0, align 4
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define void @foo(i32 signext %var1) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: addis r4, r2, res@toc@ha
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: rlwinm r3, r3, 14, 0, 12
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; CHECK-NEXT: stw r3, res@toc@l(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp eq i32 %var1, 1
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%conv = zext i1 %cmp to i32
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%shl = shl nuw nsw i32 %conv, 19
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store i32 %shl, ptr @res, align 4
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ret void
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}
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define void @foo_multiple_use(i32 signext %var1) {
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; CHECK-LABEL: foo_multiple_use:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: addis r5, r2, res2@toc@ha
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r4, r3, 5
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; CHECK-NEXT: rlwinm r3, r3, 14, 0, 12
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; CHECK-NEXT: stw r4, res2@toc@l(r5)
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; CHECK-NEXT: addis r4, r2, res@toc@ha
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; CHECK-NEXT: stw r3, res@toc@l(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp eq i32 %var1, 1
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%conv = zext i1 %cmp to i32
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store i32 %conv, ptr @res2, align 4
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%shl = shl nuw nsw i32 %conv, 19
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store i32 %shl, ptr @res, align 4
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ret void
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}
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