c42f0a6e64
The intent of this patch is to make upper halves of SPE SuperRegs(s0,..,s31) as artificial regs, similar to how X86 has done it. And emit store /reload instructions for the required halves. PR : https://github.com/llvm/llvm-project/issues/57307 Reviewed By: jhibbits Differential Revision: https://reviews.llvm.org/D152437
263 lines
8.4 KiB
LLVM
263 lines
8.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names < %s -mcpu=e500 \
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; RUN: -mtriple=powerpc-unknown-linux-gnu -mattr=spe | FileCheck %s \
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; RUN: -check-prefix=SPE
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declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)
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declare i64 @llvm.experimental.constrained.fptosi.i64.f64(double, metadata)
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declare i64 @llvm.experimental.constrained.fptoui.i64.f64(double, metadata)
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declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata)
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declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata)
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declare i64 @llvm.experimental.constrained.fptosi.i64.f32(float, metadata)
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declare i64 @llvm.experimental.constrained.fptoui.i64.f32(float, metadata)
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declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata)
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declare double @llvm.experimental.constrained.sitofp.f64.i32(i32, metadata, metadata)
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declare double @llvm.experimental.constrained.sitofp.f64.i64(i64, metadata, metadata)
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declare double @llvm.experimental.constrained.uitofp.f64.i32(i32, metadata, metadata)
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declare double @llvm.experimental.constrained.uitofp.f64.i64(i64, metadata, metadata)
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declare float @llvm.experimental.constrained.sitofp.f32.i64(i64, metadata, metadata)
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declare float @llvm.experimental.constrained.sitofp.f32.i32(i32, metadata, metadata)
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declare float @llvm.experimental.constrained.uitofp.f32.i32(i32, metadata, metadata)
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declare float @llvm.experimental.constrained.uitofp.f32.i64(i64, metadata, metadata)
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define i32 @d_to_i32(double %m) #0 {
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; SPE-LABEL: d_to_i32:
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; SPE: # %bb.0: # %entry
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; SPE-NEXT: evmergelo r3, r3, r4
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; SPE-NEXT: efdctsiz r3, r3
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; SPE-NEXT: blr
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entry:
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%conv = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %m, metadata !"fpexcept.strict") #0
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ret i32 %conv
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}
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define i64 @d_to_i64(double %m) #0 {
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; SPE-LABEL: d_to_i64:
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; SPE: # %bb.0: # %entry
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; SPE-NEXT: mflr r0
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; SPE-NEXT: stwu r1, -16(r1)
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; SPE-NEXT: stw r0, 20(r1)
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; SPE-NEXT: .cfi_def_cfa_offset 16
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; SPE-NEXT: .cfi_offset lr, 4
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; SPE-NEXT: evmergelo r4, r3, r4
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; SPE-NEXT: evmergehi r3, r4, r4
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; SPE-NEXT: bl __fixdfdi
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; SPE-NEXT: lwz r0, 20(r1)
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; SPE-NEXT: addi r1, r1, 16
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; SPE-NEXT: mtlr r0
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; SPE-NEXT: blr
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entry:
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%conv = call i64 @llvm.experimental.constrained.fptosi.i64.f64(double %m, metadata !"fpexcept.strict") #0
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ret i64 %conv
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}
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define i64 @d_to_u64(double %m) #0 {
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; SPE-LABEL: d_to_u64:
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; SPE: # %bb.0: # %entry
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; SPE-NEXT: mflr r0
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; SPE-NEXT: stwu r1, -16(r1)
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; SPE-NEXT: stw r0, 20(r1)
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; SPE-NEXT: .cfi_def_cfa_offset 16
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; SPE-NEXT: .cfi_offset lr, 4
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; SPE-NEXT: evmergelo r4, r3, r4
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; SPE-NEXT: evmergehi r3, r4, r4
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; SPE-NEXT: bl __fixunsdfdi
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; SPE-NEXT: lwz r0, 20(r1)
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; SPE-NEXT: addi r1, r1, 16
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; SPE-NEXT: mtlr r0
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; SPE-NEXT: blr
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entry:
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%conv = call i64 @llvm.experimental.constrained.fptoui.i64.f64(double %m, metadata !"fpexcept.strict") #0
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ret i64 %conv
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}
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define zeroext i32 @d_to_u32(double %m) #0 {
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; SPE-LABEL: d_to_u32:
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; SPE: # %bb.0: # %entry
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; SPE-NEXT: evmergelo r3, r3, r4
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; SPE-NEXT: efdctuiz r3, r3
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; SPE-NEXT: blr
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entry:
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%conv = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %m, metadata !"fpexcept.strict") #0
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ret i32 %conv
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}
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define signext i32 @f_to_i32(float %m) #0 {
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; SPE-LABEL: f_to_i32:
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; SPE: # %bb.0: # %entry
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; SPE-NEXT: efsctsiz r3, r3
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; SPE-NEXT: blr
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entry:
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%conv = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %m, metadata !"fpexcept.strict") #0
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ret i32 %conv
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}
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define i64 @f_to_i64(float %m) #0 {
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; SPE-LABEL: f_to_i64:
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; SPE: # %bb.0: # %entry
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; SPE-NEXT: mflr r0
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; SPE-NEXT: stwu r1, -16(r1)
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; SPE-NEXT: stw r0, 20(r1)
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; SPE-NEXT: .cfi_def_cfa_offset 16
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; SPE-NEXT: .cfi_offset lr, 4
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; SPE-NEXT: bl __fixsfdi
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; SPE-NEXT: lwz r0, 20(r1)
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; SPE-NEXT: addi r1, r1, 16
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; SPE-NEXT: mtlr r0
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; SPE-NEXT: blr
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entry:
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%conv = call i64 @llvm.experimental.constrained.fptosi.i64.f32(float %m, metadata !"fpexcept.strict") #0
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ret i64 %conv
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}
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define i64 @f_to_u64(float %m) #0 {
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; SPE-LABEL: f_to_u64:
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; SPE: # %bb.0: # %entry
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; SPE-NEXT: mflr r0
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; SPE-NEXT: stwu r1, -16(r1)
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; SPE-NEXT: stw r0, 20(r1)
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; SPE-NEXT: .cfi_def_cfa_offset 16
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; SPE-NEXT: .cfi_offset lr, 4
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; SPE-NEXT: bl __fixunssfdi
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; SPE-NEXT: lwz r0, 20(r1)
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; SPE-NEXT: addi r1, r1, 16
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; SPE-NEXT: mtlr r0
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; SPE-NEXT: blr
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entry:
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%conv = call i64 @llvm.experimental.constrained.fptoui.i64.f32(float %m, metadata !"fpexcept.strict") #0
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ret i64 %conv
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}
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define zeroext i32 @f_to_u32(float %m) #0 {
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; SPE-LABEL: f_to_u32:
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; SPE: # %bb.0: # %entry
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; SPE-NEXT: efsctuiz r3, r3
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; SPE-NEXT: blr
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entry:
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%conv = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %m, metadata !"fpexcept.strict") #0
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ret i32 %conv
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}
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define double @i32_to_d(i32 signext %m) #0 {
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; SPE-LABEL: i32_to_d:
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; SPE: # %bb.0: # %entry
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; SPE-NEXT: efdcfsi r4, r3
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; SPE-NEXT: evmergehi r3, r4, r4
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; SPE-NEXT: blr
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entry:
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%conv = tail call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
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ret double %conv
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}
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define double @i64_to_d(i64 %m) #0 {
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; SPE-LABEL: i64_to_d:
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; SPE: # %bb.0: # %entry
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; SPE-NEXT: mflr r0
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; SPE-NEXT: stwu r1, -16(r1)
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; SPE-NEXT: stw r0, 20(r1)
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; SPE-NEXT: .cfi_def_cfa_offset 16
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; SPE-NEXT: .cfi_offset lr, 4
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; SPE-NEXT: bl __floatdidf
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; SPE-NEXT: evmergelo r4, r3, r4
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; SPE-NEXT: evmergehi r3, r4, r4
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; SPE-NEXT: lwz r0, 20(r1)
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; SPE-NEXT: addi r1, r1, 16
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; SPE-NEXT: mtlr r0
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; SPE-NEXT: blr
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entry:
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%conv = tail call double @llvm.experimental.constrained.sitofp.f64.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
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ret double %conv
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}
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define double @u32_to_d(i32 zeroext %m) #0 {
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; SPE-LABEL: u32_to_d:
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; SPE: # %bb.0: # %entry
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; SPE-NEXT: efdcfui r4, r3
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; SPE-NEXT: evmergehi r3, r4, r4
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; SPE-NEXT: blr
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entry:
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%conv = tail call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
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ret double %conv
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}
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define double @u64_to_d(i64 %m) #0 {
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; SPE-LABEL: u64_to_d:
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; SPE: # %bb.0: # %entry
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; SPE-NEXT: mflr r0
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; SPE-NEXT: stwu r1, -16(r1)
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; SPE-NEXT: stw r0, 20(r1)
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; SPE-NEXT: .cfi_def_cfa_offset 16
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; SPE-NEXT: .cfi_offset lr, 4
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; SPE-NEXT: bl __floatundidf
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; SPE-NEXT: evmergelo r4, r3, r4
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; SPE-NEXT: evmergehi r3, r4, r4
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; SPE-NEXT: lwz r0, 20(r1)
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; SPE-NEXT: addi r1, r1, 16
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; SPE-NEXT: mtlr r0
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; SPE-NEXT: blr
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entry:
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%conv = tail call double @llvm.experimental.constrained.uitofp.f64.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
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ret double %conv
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}
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define float @i32_to_f(i32 signext %m) #0 {
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; SPE-LABEL: i32_to_f:
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; SPE: # %bb.0: # %entry
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; SPE-NEXT: efscfsi r3, r3
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; SPE-NEXT: blr
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entry:
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%conv = tail call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
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ret float %conv
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}
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define float @i64_to_f(i64 %m) #0 {
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; SPE-LABEL: i64_to_f:
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; SPE: # %bb.0: # %entry
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; SPE-NEXT: mflr r0
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; SPE-NEXT: stwu r1, -16(r1)
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; SPE-NEXT: stw r0, 20(r1)
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; SPE-NEXT: .cfi_def_cfa_offset 16
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; SPE-NEXT: .cfi_offset lr, 4
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; SPE-NEXT: bl __floatdisf
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; SPE-NEXT: lwz r0, 20(r1)
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; SPE-NEXT: addi r1, r1, 16
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; SPE-NEXT: mtlr r0
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; SPE-NEXT: blr
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entry:
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%conv = tail call float @llvm.experimental.constrained.sitofp.f32.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
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ret float %conv
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}
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define float @u32_to_f(i32 zeroext %m) #0 {
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; SPE-LABEL: u32_to_f:
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; SPE: # %bb.0: # %entry
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; SPE-NEXT: efscfui r3, r3
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; SPE-NEXT: blr
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entry:
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%conv = tail call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
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ret float %conv
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}
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define float @u64_to_f(i64 %m) #0 {
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; SPE-LABEL: u64_to_f:
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; SPE: # %bb.0: # %entry
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; SPE-NEXT: mflr r0
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; SPE-NEXT: stwu r1, -16(r1)
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; SPE-NEXT: stw r0, 20(r1)
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; SPE-NEXT: .cfi_def_cfa_offset 16
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; SPE-NEXT: .cfi_offset lr, 4
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; SPE-NEXT: bl __floatundisf
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; SPE-NEXT: lwz r0, 20(r1)
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; SPE-NEXT: addi r1, r1, 16
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; SPE-NEXT: mtlr r0
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; SPE-NEXT: blr
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entry:
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%conv = tail call float @llvm.experimental.constrained.uitofp.f32.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
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ret float %conv
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}
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attributes #0 = { strictfp }
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