c42f0a6e64
The intent of this patch is to make upper halves of SPE SuperRegs(s0,..,s31) as artificial regs, similar to how X86 has done it. And emit store /reload instructions for the required halves. PR : https://github.com/llvm/llvm-project/issues/57307 Reviewed By: jhibbits Differential Revision: https://reviews.llvm.org/D152437
40 lines
1.1 KiB
LLVM
40 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
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; RUN: -mattr=+spe | FileCheck %s
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define i32 @test_f32(float %x) {
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; CHECK-LABEL: test_f32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stwu 1, -16(1)
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset r31, -4
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; CHECK-NEXT: stw 3, 8(1)
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; CHECK-NEXT: stw 31, 12(1) # 4-byte Folded Spill
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; CHECK-NEXT: lwz 3, 8(1)
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; CHECK-NEXT: #APP
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; CHECK-NEXT: efsctsi 31, 3
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: mr 3, 31
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; CHECK-NEXT: lwz 31, 12(1) # 4-byte Folded Reload
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; CHECK-NEXT: addi 1, 1, 16
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; CHECK-NEXT: blr
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entry:
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%0 = call i32 asm sideeffect "efsctsi $0, $1", "={f31},f"(float %x)
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ret i32 %0
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}
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define i32 @test_f64(double %x) {
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; CHECK-LABEL: test_f64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: evmergelo 3, 3, 4
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; CHECK-NEXT: #APP
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; CHECK-NEXT: efdctsi 0, 3
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: mr 3, 0
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; CHECK-NEXT: blr
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entry:
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%0 = call i32 asm sideeffect "efdctsi $0, $1", "={f0},d"(double %x)
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ret i32 %0
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}
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