7b7b0b95b2
For some reason, isOperationLegalOrCustom is not the same as isOperationLegal || isOperationCustom. Unfortunately, it checks if the type is legal which makes it uesless for custom lowering on non-legal types (which is always ppcf128). Really the DAG builder shouldn't be going to expand this in the builder, it makes it difficult to work with. It's only here to work around the DAG requiring legal integer types the same size as the FP type after type legalization.
448 lines
12 KiB
LLVM
448 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs -o - %s | FileCheck %s
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define i1 @isnan_float(float %x) nounwind {
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; CHECK-LABEL: isnan_float:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcsp 0, 1, 64
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: iseleq 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 3) ; nan
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ret i1 %1
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}
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define i1 @isnan_double(double %x) nounwind {
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; CHECK-LABEL: isnan_double:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcdp 0, 1, 64
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: iseleq 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f64(double %x, i32 3) ; nan
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ret i1 %1
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}
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define i1 @isnan_ppc_fp128(ppc_fp128 %x) nounwind {
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; CHECK-LABEL: isnan_ppc_fp128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcdp 0, 1, 64
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: iseleq 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %x, i32 3) ; nan
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ret i1 %1
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}
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define i1 @isnan_f128(fp128 %x) nounwind {
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; CHECK-LABEL: isnan_f128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcqp 0, 2, 64
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: iseleq 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 3) ; nan
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ret i1 %1
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}
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define i1 @isnan_float_strictfp(float %x) strictfp nounwind {
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; CHECK-LABEL: isnan_float_strictfp:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcsp 0, 1, 64
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: iseleq 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 3) strictfp ; nan
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ret i1 %1
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}
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define i1 @isnan_double_strictfp(double %x) strictfp nounwind {
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; CHECK-LABEL: isnan_double_strictfp:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcdp 0, 1, 64
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: iseleq 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f64(double %x, i32 3) strictfp ; nan
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ret i1 %1
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}
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define i1 @isnan_ppc_fp128_strictfp(ppc_fp128 %x) strictfp nounwind {
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; CHECK-LABEL: isnan_ppc_fp128_strictfp:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcdp 0, 1, 64
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: iseleq 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %x, i32 3) strictfp ; nan
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ret i1 %1
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}
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define i1 @isnan_f128_strictfp(fp128 %x) strictfp nounwind {
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; CHECK-LABEL: isnan_f128_strictfp:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcqp 0, 2, 64
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: iseleq 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 3) strictfp ; nan
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ret i1 %1
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}
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define i1 @isinf_float(float %x) nounwind {
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; CHECK-LABEL: isinf_float:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcsp 0, 1, 48
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: iseleq 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 516) ; 0x204 = "inf"
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ret i1 %1
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}
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define i1 @isinf_ppc_fp128(ppc_fp128 %x) nounwind {
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; CHECK-LABEL: isinf_ppc_fp128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcdp 0, 1, 48
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: iseleq 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %x, i32 516) ; 0x204 = "inf"
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ret i1 %1
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}
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define i1 @isinf_f128(fp128 %x) nounwind {
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; CHECK-LABEL: isinf_f128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcqp 0, 2, 48
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: iseleq 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 516) ; 0x204 = "inf"
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ret i1 %1
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}
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define i1 @isfinite_float(float %x) nounwind {
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; CHECK-LABEL: isfinite_float:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcsp 0, 1, 112
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: iseleq 3, 0, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 504) ; 0x1f8 = "finite"
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ret i1 %1
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}
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define i1 @isfinite_f128(fp128 %x) nounwind {
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; CHECK-LABEL: isfinite_f128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcqp 0, 2, 112
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: iseleq 3, 0, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 504) ; 0x1f8 = "finite"
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ret i1 %1
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}
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define i1 @isnormal_float(float %x) nounwind {
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; CHECK-LABEL: isnormal_float:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcsp 0, 1, 127
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: iseleq 3, 0, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 264) ; 0x108 = "normal"
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ret i1 %1
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}
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define i1 @isnormal_f128(fp128 %x) nounwind {
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; CHECK-LABEL: isnormal_f128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcqp 0, 2, 127
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: iseleq 3, 0, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 264) ; 0x108 = "normal"
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ret i1 %1
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}
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define i1 @issubnormal_float(float %x) nounwind {
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; CHECK-LABEL: issubnormal_float:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcsp 0, 1, 3
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: iseleq 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 144) ; 0x90 = "subnormal"
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ret i1 %1
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}
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define i1 @issubnormal_f128(fp128 %x) nounwind {
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; CHECK-LABEL: issubnormal_f128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcqp 0, 2, 3
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: iseleq 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 144) ; 0x90 = "subnormal"
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ret i1 %1
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}
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define i1 @iszero_float(float %x) nounwind {
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; CHECK-LABEL: iszero_float:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcsp 0, 1, 12
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: iseleq 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 96) ; 0x60 = "zero"
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ret i1 %1
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}
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define i1 @iszero_f128(fp128 %x) nounwind {
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; CHECK-LABEL: iszero_f128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcqp 0, 2, 12
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: iseleq 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 96) ; 0x60 = "zero"
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ret i1 %1
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}
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define i1 @issnan_float(float %x) nounwind {
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; CHECK-LABEL: issnan_float:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xscvdpspn 0, 1
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; CHECK-NEXT: xststdcsp 1, 1, 64
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; CHECK-NEXT: mffprwz 3, 0
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; CHECK-NEXT: andis. 3, 3, 64
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: crnand 20, 6, 2
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; CHECK-NEXT: isel 3, 0, 3, 20
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 1)
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ret i1 %1
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}
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define i1 @issnan_double(double %x) nounwind {
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; CHECK-LABEL: issnan_double:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mffprd 3, 1
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; CHECK-NEXT: xststdcdp 1, 1, 64
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; CHECK-NEXT: rldicl 3, 3, 32, 32
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; CHECK-NEXT: andis. 3, 3, 8
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: crnand 20, 6, 2
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; CHECK-NEXT: isel 3, 0, 3, 20
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f64(double %x, i32 1)
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ret i1 %1
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}
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define i1 @issnan_fp128(fp128 %x) nounwind {
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; CHECK-LABEL: issnan_fp128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li 3, 12
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; CHECK-NEXT: xststdcqp 1, 2, 64
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; CHECK-NEXT: vextuwrx 3, 3, 2
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; CHECK-NEXT: andi. 3, 3, 32768
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: crnand 20, 6, 2
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; CHECK-NEXT: isel 3, 0, 3, 20
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 1)
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ret i1 %1
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}
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define i1 @issnan_ppc_fp128(ppc_fp128 %x) nounwind {
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; CHECK-LABEL: issnan_ppc_fp128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mffprd 3, 1
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; CHECK-NEXT: xststdcdp 1, 1, 64
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; CHECK-NEXT: rldicl 3, 3, 32, 32
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; CHECK-NEXT: andis. 3, 3, 8
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: crnand 20, 6, 2
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; CHECK-NEXT: isel 3, 0, 3, 20
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %x, i32 1)
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ret i1 %1
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}
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define i1 @isqnan_float(float %x) nounwind {
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; CHECK-LABEL: isqnan_float:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xscvdpspn 0, 1
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; CHECK-NEXT: xststdcsp 1, 1, 64
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; CHECK-NEXT: mffprwz 3, 0
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; CHECK-NEXT: srwi 3, 3, 22
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; CHECK-NEXT: andi. 3, 3, 1
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: crnand 20, 6, 1
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; CHECK-NEXT: isel 3, 0, 3, 20
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 2)
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ret i1 %1
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}
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define i1 @isqnan_double(double %x) nounwind {
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; CHECK-LABEL: isqnan_double:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mffprd 3, 1
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; CHECK-NEXT: xststdcdp 1, 1, 64
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; CHECK-NEXT: rldicl 3, 3, 13, 51
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; CHECK-NEXT: andi. 3, 3, 1
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: crnand 20, 6, 1
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; CHECK-NEXT: isel 3, 0, 3, 20
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f64(double %x, i32 2)
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ret i1 %1
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}
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define i1 @isqnan_fp128(fp128 %x) nounwind {
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; CHECK-LABEL: isqnan_fp128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li 3, 12
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; CHECK-NEXT: xststdcqp 1, 2, 64
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; CHECK-NEXT: vextuwrx 3, 3, 2
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; CHECK-NEXT: srwi 3, 3, 15
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; CHECK-NEXT: andi. 3, 3, 1
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: crnand 20, 6, 1
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; CHECK-NEXT: isel 3, 0, 3, 20
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 2)
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ret i1 %1
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}
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define i1 @isqnan_ppc_fp128(ppc_fp128 %x) nounwind {
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; CHECK-LABEL: isqnan_ppc_fp128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mffprd 3, 1
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; CHECK-NEXT: xststdcdp 1, 1, 64
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; CHECK-NEXT: rldicl 3, 3, 13, 51
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; CHECK-NEXT: andi. 3, 3, 1
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: crnand 20, 6, 1
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; CHECK-NEXT: isel 3, 0, 3, 20
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %x, i32 2)
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ret i1 %1
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}
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define i1 @isposzero_double(double %x) nounwind {
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; CHECK-LABEL: isposzero_double:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcdp 0, 1, 8
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: iseleq 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f64(double %x, i32 64)
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ret i1 %1
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}
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define i1 @isnegzero_double(double %x) nounwind {
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; CHECK-LABEL: isnegzero_double:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcdp 0, 1, 4
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: iseleq 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f64(double %x, i32 32)
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ret i1 %1
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}
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define i1 @isposnormal_double(double %x) nounwind {
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; CHECK-LABEL: isposnormal_double:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcdp 0, 1, 127
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: cror 20, 0, 2
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; CHECK-NEXT: isel 3, 0, 3, 20
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f64(double %x, i32 256)
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ret i1 %1
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}
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define i1 @isnegnormal_double(double %x) nounwind {
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; CHECK-LABEL: isnegnormal_double:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcdp 0, 1, 127
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: crorc 20, 2, 0
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; CHECK-NEXT: isel 3, 0, 3, 20
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f64(double %x, i32 8)
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ret i1 %1
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}
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define i1 @isnormal_double(double %x) nounwind {
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; CHECK-LABEL: isnormal_double:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xststdcdp 0, 1, 127
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: iseleq 3, 0, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f64(double %x, i32 264)
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ret i1 %1
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}
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define i1 @isclass_00d_double(double %x) nounwind {
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; CHECK-LABEL: isclass_00d_double:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mffprd 3, 1
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; CHECK-NEXT: xststdcdp 0, 1, 127
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; CHECK-NEXT: xststdcdp 1, 1, 64
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; CHECK-NEXT: rldicl 3, 3, 32, 32
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; CHECK-NEXT: crandc 20, 0, 2
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; CHECK-NEXT: andis. 3, 3, 8
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: crand 21, 6, 2
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; CHECK-NEXT: xststdcdp 0, 1, 16
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; CHECK-NEXT: cror 21, 2, 21
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; CHECK-NEXT: crnor 20, 21, 20
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; CHECK-NEXT: isel 3, 0, 3, 20
|
|
; CHECK-NEXT: blr
|
|
%1 = call i1 @llvm.is.fpclass.f64(double %x, i32 13)
|
|
ret i1 %1
|
|
}
|
|
|
|
define i1 @isclass_1c0_float(float %x) nounwind {
|
|
; CHECK-LABEL: isclass_1c0_float:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: xststdcsp 0, 1, 127
|
|
; CHECK-NEXT: li 3, 1
|
|
; CHECK-NEXT: crnor 20, 0, 2
|
|
; CHECK-NEXT: xststdcsp 0, 1, 10
|
|
; CHECK-NEXT: crnor 20, 2, 20
|
|
; CHECK-NEXT: isel 3, 0, 3, 20
|
|
; CHECK-NEXT: blr
|
|
%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 448)
|
|
ret i1 %1
|
|
}
|
|
|
|
declare i1 @llvm.is.fpclass.f32(float, i32)
|
|
declare i1 @llvm.is.fpclass.f64(double, i32)
|
|
declare i1 @llvm.is.fpclass.ppcf128(ppc_fp128, i32)
|
|
declare i1 @llvm.is.fpclass.f128(fp128, i32)
|