427fb35192
The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, amyk, nikic, PowerPC Differential Revision: https://reviews.llvm.org/D135470
190 lines
5.9 KiB
LLVM
190 lines
5.9 KiB
LLVM
; XFAIL: *
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; Function Attrs: nounwind
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define signext i32 @logic_ne_32(i32 signext %a, i32 signext %b, i32 signext %c) {
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; CHECK-LABEL: logic_ne_32:
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; CHECK: xor r7, r3, r4
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; CHECK-NEXT: li r6, 55
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; CHECK-NEXT: xor r5, r5, r6
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; CHECK-NEXT: or r7, r7, r4
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; CHECK-NEXT: cntlzw r5, r5
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; CHECK-NEXT: cntlzw r6, r7
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; CHECK-NEXT: srwi r6, r6, 5
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; CHECK-NEXT: srwi r5, r5, 5
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; CHECK-NEXT: or. r5, r6, r5
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; CHECK-NEXT: bc 4, gt
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entry:
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%tobool = icmp eq i32 %a, %b
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%tobool1 = icmp eq i32 %b, 0
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%or.cond = and i1 %tobool, %tobool1
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%tobool3 = icmp eq i32 %c, 55
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%or.cond5 = or i1 %or.cond, %tobool3
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br i1 %or.cond5, label %if.end, label %if.then
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if.then: ; preds = %entry
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%call = tail call signext i32 @foo(i32 signext %a) #2
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br label %return
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if.end: ; preds = %entry
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%call4 = tail call signext i32 @bar(i32 signext %b) #2
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br label %return
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return: ; preds = %if.end, %if.then
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%retval.0 = phi i32 [ %call4, %if.end ], [ %call, %if.then ]
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ret i32 %retval.0
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}
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define void @neg_truncate_i32_eq(ptr %ptr) {
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; CHECK-LABEL: neg_truncate_i32_eq:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lwz r3, 0(r3)
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; CHECK-NEXT: rldicl. r3, r3, 0, 63
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; CHECK-NEXT: bclr 12, eq, 0
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; CHECK-NEXT: # %bb.1: # %if.end29.thread136
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entry:
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%0 = load i32, ptr %ptr, align 4
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%rem17127 = and i32 %0, 1
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%cmp18 = icmp eq i32 %rem17127, 0
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br label %if.else
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if.else: ; preds = %entry
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br i1 %cmp18, label %if.end29, label %if.end29.thread136
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if.end29.thread136: ; preds = %if.else
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unreachable
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if.end29: ; preds = %if.else
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ret void
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}
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; Function Attrs: nounwind
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define i64 @logic_eq_64(i64 %a, i64 %b, i64 %c) {
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; CHECK-LABEL: logic_eq_64:
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; CHECK: xor r7, r3, r4
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; CHECK-NEXT: li r6, 55
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; CHECK-NEXT: xor r5, r5, r6
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; CHECK-NEXT: or r7, r7, r4
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; CHECK-NEXT: cntlzd r6, r7
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; CHECK-NEXT: cntlzd r5, r5
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; CHECK-NEXT: rldicl r6, r6, 58, 63
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; CHECK-NEXT: rldicl r5, r5, 58, 63
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; CHECK-NEXT: or. r5, r6, r5
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; CHECK-NEXT: bc 4, gt
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entry:
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%tobool = icmp eq i64 %a, %b
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%tobool1 = icmp eq i64 %b, 0
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%or.cond = and i1 %tobool, %tobool1
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%tobool3 = icmp eq i64 %c, 55
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%or.cond5 = or i1 %or.cond, %tobool3
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br i1 %or.cond5, label %if.end, label %if.then
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if.then: ; preds = %entry
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%call = tail call i64 @foo64(i64 %a) #2
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br label %return
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if.end: ; preds = %entry
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%call4 = tail call i64 @bar64(i64 %b) #2
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br label %return
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return: ; preds = %if.end, %if.then
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%retval.0 = phi i64 [ %call4, %if.end ], [ %call, %if.then ]
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ret i64 %retval.0
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}
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define void @neg_truncate_i64_eq(ptr %ptr) {
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; CHECK-LABEL: neg_truncate_i64_eq:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ld r3, 0(r3)
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; CHECK-NEXT: rldicl. r3, r3, 0, 63
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; CHECK-NEXT: bclr 12, eq, 0
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; CHECK-NEXT: # %bb.1: # %if.end29.thread136
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entry:
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%0 = load i64, ptr %ptr, align 4
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%rem17127 = and i64 %0, 1
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%cmp18 = icmp eq i64 %rem17127, 0
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br label %if.else
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if.else: ; preds = %entry
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br i1 %cmp18, label %if.end29, label %if.end29.thread136
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if.end29.thread136: ; preds = %if.else
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unreachable
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if.end29: ; preds = %if.else
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ret void
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}
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; Function Attrs: nounwind
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define i64 @logic_ne_64(i64 %a, i64 %b, i64 %c) {
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; CHECK-LABEL: logic_ne_64:
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; CHECK: xor r7, r3, r4
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; CHECK-NEXT: li r6, 55
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; CHECK-NEXT: addic r8, r7, -1
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; CHECK-NEXT: xor r5, r5, r6
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; CHECK-NEXT: subfe r7, r8, r7
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; CHECK-NEXT: cntlzd r5, r5
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; CHECK-NEXT: addic r12, r4, -1
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; CHECK-NEXT: rldicl r5, r5, 58, 63
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; CHECK-NEXT: subfe r6, r12, r4
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; CHECK-NEXT: and r6, r7, r6
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; CHECK-NEXT: or. r5, r6, r5
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; CHECK-NEXT: bc 4, gt
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entry:
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%tobool = icmp ne i64 %a, %b
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%tobool1 = icmp ne i64 %b, 0
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%or.cond = and i1 %tobool, %tobool1
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%tobool3 = icmp eq i64 %c, 55
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%or.cond5 = or i1 %or.cond, %tobool3
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br i1 %or.cond5, label %if.end, label %if.then
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if.then: ; preds = %entry
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%call = tail call i64 @foo64(i64 %a) #2
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br label %return
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if.end: ; preds = %entry
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%call4 = tail call i64 @bar64(i64 %b) #2
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br label %return
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return: ; preds = %if.end, %if.then
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%retval.0 = phi i64 [ %call4, %if.end ], [ %call, %if.then ]
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ret i64 %retval.0
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}
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define void @neg_truncate_i64_ne(ptr %ptr) {
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; CHECK-LABEL: neg_truncate_i64_ne:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ld r3, 0(r3)
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; CHECK-NEXT: andi. r3, r3, 1
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; CHECK-NEXT: bclr 12, gt, 0
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; CHECK-NEXT: # %bb.1: # %if.end29.thread136
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entry:
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%0 = load i64, ptr %ptr, align 4
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%rem17127 = and i64 %0, 1
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%cmp18 = icmp ne i64 %rem17127, 0
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br label %if.else
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if.else: ; preds = %entry
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br i1 %cmp18, label %if.end29, label %if.end29.thread136
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if.end29.thread136: ; preds = %if.else
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unreachable
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if.end29: ; preds = %if.else
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ret void
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}
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declare signext i32 @foo(i32 signext)
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declare signext i32 @bar(i32 signext)
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declare i64 @foo64(i64)
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declare i64 @bar64(i64)
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