427fb35192
The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, amyk, nikic, PowerPC Differential Revision: https://reviews.llvm.org/D135470
49 lines
1.2 KiB
LLVM
49 lines
1.2 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
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; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
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; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE
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@a = common global i32 0
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define zeroext i32 @test_load() {
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entry:
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%0 = load i32, ptr @a
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ret i32 %0
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}
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; SMALL-LABEL: .test_load:{{$}}
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; SMALL: ld [[REG1:[0-9]+]], L..C0(2)
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; SMALL: lwz [[REG2:[0-9]+]], 0([[REG1]])
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; SMALL: blr
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; LARGE-LABEL: .test_load:{{$}}
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; LARGE: addis [[REG1:[0-9]+]], L..C0@u(2)
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; LARGE: ld [[REG2:[0-9]+]], L..C0@l([[REG1]])
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; LARGE: lwz [[REG3:[0-9]+]], 0([[REG2]])
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; LARGE: blr
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@b = common global i32 0
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define void @test_store(i32 zeroext %0) {
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store i32 %0, ptr @b
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ret void
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}
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; SMALL-LABEL: .test_store:{{$}}
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; SMALL: ld [[REG1:[0-9]+]], L..C1(2)
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; SMALL: stw [[REG2:[0-9]+]], 0([[REG1]])
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; SMALL: blr
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; LARGE-LABEL: .test_store:{{$}}
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; LARGE: addis [[REG1:[0-9]+]], L..C1@u(2)
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; LARGE: ld [[REG2:[0-9]+]], L..C1@l([[REG1]])
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; LARGE: stw [[REG3:[0-9]+]], 0([[REG2]])
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; LARGE: blr
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; SMALL: .tc a[TC],a
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; SMALL: .tc b[TC],b
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; LARGE: .tc a[TE],a
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; LARGE: .tc b[TE],b
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