23b3203113
The patch fixed a bug introduced patch [[PowePC] using MTVSRBMI instruction instead of constant pool in power10+](https://github.com/llvm/llvm-project/pull/144084#top). The issue arose because the layout of vector register elements differs between little-endian and big-endian modes — specifically, the elements appear in reverse order. This led to incorrect behavior when loading constants using MTVSRBMI in big-endian configurations.
89 lines
2.6 KiB
LLVM
89 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; Verify whether the generated assembly for the following function includes the mtvsrbmi instruction.
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; vector unsigned char v00FF()
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; {
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; vector unsigned char x = { 0xFF, 0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0 };
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; return x;
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; }
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; vector unsigned short short00FF()
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; {
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; vector unsigned short x = { 0xFF, 0,0,0, 0,0,0,0};
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; return x;
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; }
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; vector unsigned int int00FF()
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; {
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; vector unsigned int x = { 0xFF, 0,0,0};
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; return x;
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; }
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; vector unsigned long long longlong00FF()
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; {
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; vector unsigned long long x = { 0xFF, 0};
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; return x;
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; }
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; RUN: llc < %s -ppc-asm-full-reg-names -mtriple=powerpc-ibm-aix -mcpu=pwr10 -verify-machineinstrs \
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; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-BE
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; RUN: llc < %s -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr10 -verify-machineinstrs \
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; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-LE
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; CHECK-NOT: .byte 255
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; CHECK-NOT: .byte 0
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define dso_local noundef range(i8 -1, 1) <16 x i8> @_Z5v00FFv() {
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; CHECK-BE-LABEL: _Z5v00FFv:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: mtvsrbmi v2, 32768
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; CHECK-BE-NEXT: blr
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;
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; CHECK-LE-LABEL: _Z5v00FFv:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: mtvsrbmi v2, 1
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; CHECK-LE-NEXT: blr
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entry:
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ret <16 x i8> <i8 -1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
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}
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define dso_local noundef range(i16 0, 256) <8 x i16> @_Z9short00FFv() {
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; CHECK-BE-LABEL: _Z9short00FFv:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: mtvsrbmi v2, 16384
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; CHECK-BE-NEXT: blr
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;
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; CHECK-LE-LABEL: _Z9short00FFv:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: mtvsrbmi v2, 1
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; CHECK-LE-NEXT: blr
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entry:
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ret <8 x i16> <i16 255, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
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}
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define dso_local noundef range(i32 0, 256) <4 x i32> @_Z7int00FFv() {
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; CHECK-BE-LABEL: _Z7int00FFv:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: mtvsrbmi v2, 4096
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; CHECK-BE-NEXT: blr
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;
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; CHECK-LE-LABEL: _Z7int00FFv:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: mtvsrbmi v2, 1
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; CHECK-LE-NEXT: blr
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entry:
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ret <4 x i32> <i32 255, i32 0, i32 0, i32 0>
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}
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define dso_local noundef range(i64 0, 256) <2 x i64> @_Z12longlong00FFv() {
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; CHECK-BE-LABEL: _Z12longlong00FFv:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: mtvsrbmi v2, 256
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; CHECK-BE-NEXT: blr
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;
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; CHECK-LE-LABEL: _Z12longlong00FFv:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: mtvsrbmi v2, 1
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; CHECK-LE-NEXT: blr
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entry:
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ret <2 x i64> <i64 255, i64 0>
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}
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