522f34cfff
Enable all valid registers for intrinsics that read from and write to global named registers.
145 lines
4.5 KiB
LLVM
145 lines
4.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -O0 -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
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; RUN: llc -O0 -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s --check-prefix=CHECK64
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@mVal = dso_local global i32 15, align 4
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@myGVal = dso_local global i32 0, align 4
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define dso_local void @testSetIntReg(i32 noundef signext %xx) {
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; CHECK-LABEL: testSetIntReg:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mr 5, 3
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; CHECK-NEXT: blr
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;
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; CHECK64-LABEL: testSetIntReg:
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; CHECK64: # %bb.0: # %entry
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; CHECK64-NEXT: mr 5, 3
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; CHECK64-NEXT: blr
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entry:
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tail call void @llvm.write_register.i32(metadata !0, i32 %xx)
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ret void
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}
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declare void @llvm.write_register.i32(metadata, i32)
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define dso_local signext range(i32 0, 2) i32 @testCmpReg() {
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; CHECK-LABEL: testCmpReg:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lis 3, mVal@ha
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; CHECK-NEXT: lwz 3, mVal@l(3)
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; CHECK-NEXT: xori 3, 3, 15
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; CHECK-NEXT: cntlzw 3, 3
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; CHECK-NEXT: srwi 3, 3, 5
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; CHECK-NEXT: blr
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;
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; CHECK64-LABEL: testCmpReg:
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; CHECK64: # %bb.0: # %entry
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; CHECK64-NEXT: addis 3, 2, mVal@toc@ha
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; CHECK64-NEXT: addi 3, 3, mVal@toc@l
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; CHECK64-NEXT: lwz 3, 0(3)
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; CHECK64-NEXT: xori 3, 3, 15
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; CHECK64-NEXT: cntlzw 3, 3
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; CHECK64-NEXT: srwi 3, 3, 5
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; CHECK64-NEXT: extsw 3, 3
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; CHECK64-NEXT: blr
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entry:
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tail call void @llvm.write_register.i32(metadata !0, i32 15)
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%0 = load i32, ptr @mVal, align 4
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%1 = tail call i32 @llvm.read_register.i32(metadata !0)
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%cmp = icmp eq i32 %0, %1
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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declare i32 @llvm.read_register.i32(metadata)
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define dso_local void @testSetIntReg2(i32 noundef signext %xx) {
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; CHECK-LABEL: testSetIntReg2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stwu 1, -48(1)
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: .cfi_offset r23, -36
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; CHECK-NEXT: stw 23, 12(1) # 4-byte Folded Spill
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; CHECK-NEXT: mr 23, 3
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; CHECK-NEXT: lwz 23, 12(1) # 4-byte Folded Reload
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; CHECK-NEXT: addi 1, 1, 48
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; CHECK-NEXT: blr
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;
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; CHECK64-LABEL: testSetIntReg2:
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; CHECK64: # %bb.0: # %entry
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; CHECK64-NEXT: std 23, -72(1) # 8-byte Folded Spill
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; CHECK64-NEXT: mr 23, 3
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; CHECK64-NEXT: ld 23, -72(1) # 8-byte Folded Reload
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; CHECK64-NEXT: blr
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entry:
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tail call void @llvm.write_register.i32(metadata !1, i32 %xx)
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ret void
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}
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define dso_local signext i32 @testReturnReg() {
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; CHECK-LABEL: testReturnReg:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stwu 1, -48(1)
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: .cfi_offset r23, -36
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; CHECK-NEXT: stw 23, 12(1) # 4-byte Folded Spill
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; CHECK-NEXT: li 23, 125
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; CHECK-NEXT: mr 3, 23
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; CHECK-NEXT: lwz 23, 12(1) # 4-byte Folded Reload
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; CHECK-NEXT: addi 1, 1, 48
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; CHECK-NEXT: blr
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;
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; CHECK64-LABEL: testReturnReg:
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; CHECK64: # %bb.0: # %entry
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; CHECK64-NEXT: std 23, -72(1) # 8-byte Folded Spill
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; CHECK64-NEXT: li 23, 125
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; CHECK64-NEXT: extsw 3, 23
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; CHECK64-NEXT: ld 23, -72(1) # 8-byte Folded Reload
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; CHECK64-NEXT: blr
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entry:
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tail call void @llvm.write_register.i32(metadata !1, i32 125)
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%0 = tail call i32 @llvm.read_register.i32(metadata !1)
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ret i32 %0
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}
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define dso_local void @testViaASM(i32 noundef signext %xx) {
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; CHECK-LABEL: testViaASM:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stwu 1, -64(1)
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; CHECK-NEXT: .cfi_def_cfa_offset 64
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; CHECK-NEXT: .cfi_offset r20, -48
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; CHECK-NEXT: stw 20, 16(1) # 4-byte Folded Spill
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; CHECK-NEXT: mr 20, 3
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; CHECK-NEXT: #APP
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; CHECK-NEXT: addi 3, 1, 1
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: lis 4, myGVal@ha
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; CHECK-NEXT: stw 3, myGVal@l(4)
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; CHECK-NEXT: lwz 20, 16(1) # 4-byte Folded Reload
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; CHECK-NEXT: addi 1, 1, 64
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; CHECK-NEXT: blr
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;
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; CHECK64-LABEL: testViaASM:
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; CHECK64: # %bb.0: # %entry
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; CHECK64-NEXT: std 20, -96(1) # 8-byte Folded Spill
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; CHECK64-NEXT: mr 20, 3
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; CHECK64-NEXT: #APP
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; CHECK64-NEXT: addi 3, 1, 1
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; CHECK64-NEXT: #NO_APP
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; CHECK64-NEXT: addis 4, 2, myGVal@toc@ha
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; CHECK64-NEXT: addi 4, 4, myGVal@toc@l
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; CHECK64-NEXT: stw 3, 0(4)
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; CHECK64-NEXT: ld 20, -96(1) # 8-byte Folded Reload
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; CHECK64-NEXT: blr
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entry:
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tail call void @llvm.write_register.i32(metadata !2, i32 %xx)
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%0 = tail call i32 @llvm.read_register.i32(metadata !2)
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%1 = tail call i32 asm "addi $0, $2, $2", "=r,{r20},K"(i32 %0, i32 1)
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store i32 %1, ptr @myGVal, align 4
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ret void
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}
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!0 = !{!"r5"}
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!1 = !{!"r23"}
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!2 = !{!"r20"}
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