213a939a79
This is needed for architectures that actually use strict pointer arithmetic instead of integers such as AArch64 with FEAT_CPA (see https://github.com/llvm/llvm-project/pull/105669) or CHERI. Using an index as the first operand of pointer arithmetic may result in an invalid output. While there are quite a few codegen changes here, these only change the order of registers in add instructions. One MIPS combine had to be updated to handle the new node order. Reviewed By: topperc Pull Request: https://github.com/llvm/llvm-project/pull/125279
137 lines
4.7 KiB
LLVM
137 lines
4.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-min-jump-table-entries=4 < %s | FileCheck %s \
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; RUN: --check-prefix=CHECK-R
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-use-absolute-jumptables -ppc-min-jump-table-entries=4 \
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; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s \
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; RUN: --check-prefix=CHECK-A-LE
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; RUN: llc -verify-machineinstrs -target-abi=elfv2 -mtriple=powerpc64-- \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-min-jump-table-entries=4 < %s | FileCheck %s \
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; RUN: --check-prefix=CHECK-R
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; RUN: llc -verify-machineinstrs -target-abi=elfv2 -mtriple=powerpc64-- \
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; RUN: -mcpu=pwr10 -ppc-use-absolute-jumptables -ppc-min-jump-table-entries=4 \
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; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s \
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; RUN: --check-prefix=CHECK-A-BE
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; This test checks for getting relative and absolute jump table base address
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; using PC Relative addressing.
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define dso_local signext i32 @jumptable(i32 signext %param) {
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; CHECK-R-LABEL: jumptable:
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; CHECK-R: # %bb.0: # %entry
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; CHECK-R-NEXT: addi r4, r3, -1
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; CHECK-R-NEXT: cmplwi r4, 19
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; CHECK-R-NEXT: bgt cr0, .LBB0_3
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; CHECK-R-NEXT: # %bb.1: # %entry
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; CHECK-R-NEXT: rldic r4, r4, 2, 30
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; CHECK-R-NEXT: paddi r5, 0, .LJTI0_0@PCREL, 1
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; CHECK-R-NEXT: lwax r4, r5, r4
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; CHECK-R-NEXT: add r4, r5, r4
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; CHECK-R-NEXT: mtctr r4
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; CHECK-R-NEXT: bctr
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; CHECK-R-NEXT: .LBB0_2: # %sw.bb1
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; CHECK-R-NEXT: li r3, 4
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; CHECK-R-NEXT: blr
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; CHECK-R-NEXT: .LBB0_3: # %sw.default
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; CHECK-R-NEXT: li r3, -1
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; CHECK-R-NEXT: .LBB0_4: # %return
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; CHECK-R-NEXT: blr
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; CHECK-R-NEXT: .LBB0_5: # %sw.bb2
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; CHECK-R-NEXT: li r3, 9
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; CHECK-R-NEXT: blr
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; CHECK-R-NEXT: .LBB0_6: # %sw.bb3
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; CHECK-R-NEXT: li r3, 16
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; CHECK-R-NEXT: blr
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; CHECK-R-NEXT: .LBB0_7: # %sw.bb4
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; CHECK-R-NEXT: li r3, 400
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; CHECK-R-NEXT: blr
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;
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; CHECK-A-LE-LABEL: jumptable:
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; CHECK-A-LE: # %bb.0: # %entry
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; CHECK-A-LE-NEXT: addi r4, r3, -1
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; CHECK-A-LE-NEXT: cmplwi r4, 19
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; CHECK-A-LE-NEXT: bgt cr0, .LBB0_3
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; CHECK-A-LE-NEXT: # %bb.1: # %entry
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; CHECK-A-LE-NEXT: rldic r4, r4, 3, 29
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; CHECK-A-LE-NEXT: paddi r5, 0, .LJTI0_0@PCREL, 1
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; CHECK-A-LE-NEXT: ldx r4, r5, r4
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; CHECK-A-LE-NEXT: mtctr r4
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; CHECK-A-LE-NEXT: bctr
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; CHECK-A-LE-NEXT: .LBB0_2: # %sw.bb1
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; CHECK-A-LE-NEXT: li r3, 4
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; CHECK-A-LE-NEXT: blr
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; CHECK-A-LE-NEXT: .LBB0_3: # %sw.default
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; CHECK-A-LE-NEXT: li r3, -1
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; CHECK-A-LE-NEXT: .LBB0_4: # %return
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; CHECK-A-LE-NEXT: blr
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; CHECK-A-LE-NEXT: .LBB0_5: # %sw.bb2
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; CHECK-A-LE-NEXT: li r3, 9
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; CHECK-A-LE-NEXT: blr
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; CHECK-A-LE-NEXT: .LBB0_6: # %sw.bb3
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; CHECK-A-LE-NEXT: li r3, 16
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; CHECK-A-LE-NEXT: blr
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; CHECK-A-LE-NEXT: .LBB0_7: # %sw.bb4
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; CHECK-A-LE-NEXT: li r3, 400
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; CHECK-A-LE-NEXT: blr
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;
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; CHECK-A-BE-LABEL: jumptable:
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; CHECK-A-BE: # %bb.0: # %entry
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; CHECK-A-BE-NEXT: addi r4, r3, -1
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; CHECK-A-BE-NEXT: cmplwi r4, 19
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; CHECK-A-BE-NEXT: bgt cr0, .LBB0_3
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; CHECK-A-BE-NEXT: # %bb.1: # %entry
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; CHECK-A-BE-NEXT: rldic r4, r4, 2, 30
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; CHECK-A-BE-NEXT: paddi r5, 0, .LJTI0_0@PCREL, 1
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; CHECK-A-BE-NEXT: lwax r4, r5, r4
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; CHECK-A-BE-NEXT: mtctr r4
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; CHECK-A-BE-NEXT: bctr
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; CHECK-A-BE-NEXT: .LBB0_2: # %sw.bb1
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; CHECK-A-BE-NEXT: li r3, 4
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; CHECK-A-BE-NEXT: blr
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; CHECK-A-BE-NEXT: .LBB0_3: # %sw.default
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; CHECK-A-BE-NEXT: li r3, -1
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; CHECK-A-BE-NEXT: .LBB0_4: # %return
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; CHECK-A-BE-NEXT: blr
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; CHECK-A-BE-NEXT: .LBB0_5: # %sw.bb2
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; CHECK-A-BE-NEXT: li r3, 9
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; CHECK-A-BE-NEXT: blr
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; CHECK-A-BE-NEXT: .LBB0_6: # %sw.bb3
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; CHECK-A-BE-NEXT: li r3, 16
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; CHECK-A-BE-NEXT: blr
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; CHECK-A-BE-NEXT: .LBB0_7: # %sw.bb4
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; CHECK-A-BE-NEXT: li r3, 400
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; CHECK-A-BE-NEXT: blr
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entry:
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switch i32 %param, label %sw.default [
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i32 1, label %return
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i32 2, label %sw.bb1
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i32 3, label %sw.bb2
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i32 4, label %sw.bb3
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i32 20, label %sw.bb4
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]
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sw.bb1: ; preds = %entry
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br label %return
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sw.bb2: ; preds = %entry
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br label %return
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sw.bb3: ; preds = %entry
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br label %return
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sw.bb4: ; preds = %entry
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br label %return
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sw.default: ; preds = %entry
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br label %return
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return: ; preds = %entry, %sw.default, %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1
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%retval.0 = phi i32 [ -1, %sw.default ], [ 400, %sw.bb4 ], [ 16, %sw.bb3 ],
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[ 9, %sw.bb2 ], [ 4, %sw.bb1 ], [ %param, %entry ]
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ret i32 %retval.0
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}
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