llvm-project/llvm/test/CodeGen/PowerPC/ppc-32bit-build-vector.ll
Simon Pilgrim 9540a7ae82
[DAG] SimplifyMultipleUseDemandedBits - bypass ADD nodes if either operand is zero (#112588)
The dpbusd_const.ll test change is due to us losing the expanded add reduction pattern as one of the elements is known to be zero (removing one of the adds from the reduction pyramid). I don't think its of concern.

Noticed while working on #107423
2024-11-05 17:20:41 +00:00

56 lines
1.9 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc -mcpu=pwr8 < %s |\
; RUN: FileCheck %s --check-prefix=32BIT
; RUN: llc -verify-machineinstrs -mtriple=powerpc64 -mcpu=pwr8 < %s |\
; RUN: FileCheck %s --check-prefix=64BIT
define dso_local fastcc void @BuildVectorICE() unnamed_addr {
; 32BIT-LABEL: BuildVectorICE:
; 32BIT: # %bb.0: # %entry
; 32BIT-NEXT: stwu 1, -48(1)
; 32BIT-NEXT: .cfi_def_cfa_offset 48
; 32BIT-NEXT: lxvw4x 34, 0, 3
; 32BIT-NEXT: li 5, 0
; 32BIT-NEXT: addi 3, 1, 16
; 32BIT-NEXT: addi 4, 1, 32
; 32BIT-NEXT: xxspltw 35, 34, 1
; 32BIT-NEXT: .p2align 5
; 32BIT-NEXT: .LBB0_1: # %while.body
; 32BIT-NEXT: #
; 32BIT-NEXT: stw 5, 16(1)
; 32BIT-NEXT: lxvw4x 36, 0, 3
; 32BIT-NEXT: vadduwm 4, 2, 4
; 32BIT-NEXT: vadduwm 4, 4, 3
; 32BIT-NEXT: stxvw4x 36, 0, 4
; 32BIT-NEXT: lwz 5, 32(1)
; 32BIT-NEXT: b .LBB0_1
;
; 64BIT-LABEL: BuildVectorICE:
; 64BIT: # %bb.0: # %entry
; 64BIT-NEXT: lxvw4x 34, 0, 3
; 64BIT-NEXT: li 3, 0
; 64BIT-NEXT: xxspltw 35, 34, 1
; 64BIT-NEXT: .p2align 5
; 64BIT-NEXT: .LBB0_1: # %while.body
; 64BIT-NEXT: #
; 64BIT-NEXT: sldi 3, 3, 32
; 64BIT-NEXT: mtvsrd 36, 3
; 64BIT-NEXT: vadduwm 4, 2, 4
; 64BIT-NEXT: vadduwm 4, 4, 3
; 64BIT-NEXT: xxsldwi 0, 36, 36, 3
; 64BIT-NEXT: mffprwz 3, 0
; 64BIT-NEXT: b .LBB0_1
entry:
br label %while.body
while.body: ; preds = %while.body, %entry
%newelement = phi i32 [ 0, %entry ], [ %5, %while.body ]
%0 = insertelement <4 x i32> <i32 undef, i32 0, i32 0, i32 0>, i32 %newelement, i32 0
%1 = load <4 x i32>, ptr undef, align 1
%2 = add <4 x i32> %1, %0
%3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
%4 = add <4 x i32> %2, %3
%5 = extractelement <4 x i32> %4, i32 0
br label %while.body
}