dbc7665b24
Update to use REG_SEQUENCE when possible. This patch only update td pattern to utilize REG_SEQUENCE for INSERT_SUBREG for cases where it does not produce a nesting of REG_SEQUENCE. This seem to show some improvement in code gen for `llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll`. Fixes part of https://github.com/llvm/llvm-project/issues/125502
22 lines
1.0 KiB
LLVM
22 lines
1.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
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; RUN: | FileCheck %s
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define void @copy_novsrp() local_unnamed_addr {
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; CHECK-LABEL: copy_novsrp:
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; CHECK: # %bb.0: # %dmblvi_entry
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; CHECK-NEXT: xxlxor vs0, vs0, vs0
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; CHECK-NEXT: xxlxor vs3, vs3, vs3
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; CHECK-NEXT: stxv vs0, 0(0)
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dmblvi_entry:
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%0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> undef, <16 x i8> undef, <16 x i8> zeroinitializer)
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%1 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %0)
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%2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 3
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store <16 x i8> %2, ptr null, align 1
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unreachable
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}
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declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
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declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)
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