a51712751c
Utilize common API in PPCTargetParser (https://github.com/llvm/llvm-project/pull/97541) to set default CPU with same interfaces for LLC. This will update AIX default CPU to pwr7 and LoP powerppc64 default CPU to ppc64.
59 lines
1.5 KiB
LLVM
59 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs -mcpu=ppc -mtriple=powerpc64 \
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; RUN: < %s | FileCheck --check-prefix=BE %s
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; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs -mtriple=powerpc64le \
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; RUN: < %s | FileCheck --check-prefix=LE %s
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define i32 @f(...) nounwind {
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; BE-LABEL: f:
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; BE: # %bb.0: # %entry
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; BE-NEXT: li r3, 0
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; BE-NEXT: blr
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;
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; LE-LABEL: f:
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; LE: # %bb.0: # %entry
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; LE-NEXT: li r3, 0
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; LE-NEXT: blr
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entry:
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ret i32 0
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}
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define i32 @f1(...) nounwind {
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; BE-LABEL: f1:
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; BE: # %bb.0: # %entry
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; BE-NEXT: mr r11, r3
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; BE-NEXT: addi r12, r1, 48
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; BE-NEXT: li r3, 0
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; BE-NEXT: std r11, 48(r1)
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; BE-NEXT: std r4, 56(r1)
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; BE-NEXT: std r5, 64(r1)
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; BE-NEXT: std r6, 72(r1)
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; BE-NEXT: std r7, 80(r1)
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; BE-NEXT: std r8, 88(r1)
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; BE-NEXT: std r9, 96(r1)
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; BE-NEXT: std r10, 104(r1)
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; BE-NEXT: std r12, -8(r1)
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; BE-NEXT: blr
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;
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; LE-LABEL: f1:
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; LE: # %bb.0: # %entry
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; LE-NEXT: std r3, 32(r1)
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; LE-NEXT: addi r3, r1, 32
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; LE-NEXT: std r4, 40(r1)
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; LE-NEXT: std r5, 48(r1)
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; LE-NEXT: std r6, 56(r1)
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; LE-NEXT: std r7, 64(r1)
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; LE-NEXT: std r8, 72(r1)
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; LE-NEXT: std r9, 80(r1)
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; LE-NEXT: std r3, -8(r1)
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; LE-NEXT: li r3, 0
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; LE-NEXT: std r10, 88(r1)
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; LE-NEXT: blr
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entry:
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%va = alloca ptr, align 8
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call void @llvm.va_start(ptr %va)
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ret i32 0
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}
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declare void @llvm.va_start(ptr) nounwind
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