5403c59c60
The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, nikic Differential Revision: https://reviews.llvm.org/D135474
126 lines
4.2 KiB
LLVM
126 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-LE
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; RUN: llc -mtriple=powerpc64-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-BE
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@as = dso_local local_unnamed_addr global i16 0, align 2
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@bs = dso_local local_unnamed_addr global i16 0, align 2
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@ai = dso_local local_unnamed_addr global i32 0, align 4
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@bi = dso_local local_unnamed_addr global i32 0, align 4
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define dso_local void @bswapStorei64Toi32() {
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; CHECK-LABEL: bswapStorei64Toi32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis 3, 2, ai@toc@ha
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; CHECK-NEXT: addis 4, 2, bi@toc@ha
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; CHECK-NEXT: lwa 3, ai@toc@l(3)
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; CHECK-NEXT: addi 4, 4, bi@toc@l
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; CHECK-NEXT: rldicl 3, 3, 32, 32
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; CHECK-NEXT: stwbrx 3, 0, 4
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; CHECK-NEXT: blr
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; CHECK-LE-LABEL: bswapStorei64Toi32:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: addis 3, 2, ai@toc@ha
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; CHECK-LE-NEXT: addis 4, 2, bi@toc@ha
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; CHECK-LE-NEXT: lwa 3, ai@toc@l(3)
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; CHECK-LE-NEXT: addi 4, 4, bi@toc@l
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; CHECK-LE-NEXT: rldicl 3, 3, 32, 32
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; CHECK-LE-NEXT: stwbrx 3, 0, 4
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: bswapStorei64Toi32:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: addis 3, 2, ai@toc@ha
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; CHECK-BE-NEXT: addis 4, 2, bi@toc@ha
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; CHECK-BE-NEXT: lwa 3, ai@toc@l(3)
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; CHECK-BE-NEXT: addi 4, 4, bi@toc@l
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; CHECK-BE-NEXT: rldicl 3, 3, 32, 32
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; CHECK-BE-NEXT: stwbrx 3, 0, 4
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; CHECK-BE-NEXT: blr
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entry:
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%0 = load i32, ptr @ai, align 4
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%conv.i = sext i32 %0 to i64
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%or26.i = tail call i64 @llvm.bswap.i64(i64 %conv.i)
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%conv = trunc i64 %or26.i to i32
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store i32 %conv, ptr @bi, align 4
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ret void
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}
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define dso_local void @bswapStorei32Toi16() {
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; CHECK-LABEL: bswapStorei32Toi16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis 3, 2, as@toc@ha
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; CHECK-NEXT: addis 4, 2, bs@toc@ha
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; CHECK-NEXT: lha 3, as@toc@l(3)
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; CHECK-NEXT: addi 4, 4, bs@toc@l
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; CHECK-NEXT: srwi 3, 3, 16
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; CHECK-NEXT: sthbrx 3, 0, 4
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; CHECK-NEXT: blr
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; CHECK-LE-LABEL: bswapStorei32Toi16:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: addis 3, 2, as@toc@ha
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; CHECK-LE-NEXT: addis 4, 2, bs@toc@ha
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; CHECK-LE-NEXT: lha 3, as@toc@l(3)
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; CHECK-LE-NEXT: addi 4, 4, bs@toc@l
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; CHECK-LE-NEXT: srwi 3, 3, 16
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; CHECK-LE-NEXT: sthbrx 3, 0, 4
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: bswapStorei32Toi16:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: addis 3, 2, as@toc@ha
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; CHECK-BE-NEXT: addis 4, 2, bs@toc@ha
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; CHECK-BE-NEXT: lha 3, as@toc@l(3)
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; CHECK-BE-NEXT: addi 4, 4, bs@toc@l
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; CHECK-BE-NEXT: srwi 3, 3, 16
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; CHECK-BE-NEXT: sthbrx 3, 0, 4
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; CHECK-BE-NEXT: blr
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entry:
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%0 = load i16, ptr @as, align 2
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%conv.i = sext i16 %0 to i32
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%or26.i = tail call i32 @llvm.bswap.i32(i32 %conv.i)
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%conv = trunc i32 %or26.i to i16
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store i16 %conv, ptr @bs, align 2
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ret void
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}
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define dso_local void @bswapStorei64Toi16() {
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; CHECK-LABEL: bswapStorei64Toi16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis 3, 2, as@toc@ha
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; CHECK-NEXT: addis 4, 2, bs@toc@ha
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; CHECK-NEXT: lha 3, as@toc@l(3)
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; CHECK-NEXT: addi 4, 4, bs@toc@l
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; CHECK-NEXT: rldicl 3, 3, 16, 48
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; CHECK-NEXT: sthbrx 3, 0, 4
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; CHECK-NEXT: blr
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; CHECK-LE-LABEL: bswapStorei64Toi16:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: addis 3, 2, as@toc@ha
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; CHECK-LE-NEXT: addis 4, 2, bs@toc@ha
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; CHECK-LE-NEXT: lha 3, as@toc@l(3)
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; CHECK-LE-NEXT: addi 4, 4, bs@toc@l
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; CHECK-LE-NEXT: rldicl 3, 3, 16, 48
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; CHECK-LE-NEXT: sthbrx 3, 0, 4
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: bswapStorei64Toi16:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: addis 3, 2, as@toc@ha
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; CHECK-BE-NEXT: addis 4, 2, bs@toc@ha
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; CHECK-BE-NEXT: lha 3, as@toc@l(3)
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; CHECK-BE-NEXT: addi 4, 4, bs@toc@l
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; CHECK-BE-NEXT: rldicl 3, 3, 16, 48
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; CHECK-BE-NEXT: sthbrx 3, 0, 4
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; CHECK-BE-NEXT: blr
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entry:
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%0 = load i16, ptr @as, align 2
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%conv.i = sext i16 %0 to i64
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%or26.i = tail call i64 @llvm.bswap.i64(i64 %conv.i)
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%conv = trunc i64 %or26.i to i16
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store i16 %conv, ptr @bs, align 2
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ret void
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}
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declare i32 @llvm.bswap.i32(i32)
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declare i64 @llvm.bswap.i64(i64)
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