eb7d16ea25
mflr is kind of expensive on Power version smaller than 10, so we should schedule the store for the mflr's def away from mflr. In epilogue, the expensive mtlr has no user for its def, so it doesn't matter that the load and the mtlr are back-to-back. Reviewed By: RolandF Differential Revision: https://reviews.llvm.org/D137423
135 lines
5.2 KiB
LLVM
135 lines
5.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs < %s | \
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; RUN: FileCheck %s
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%0 = type { [0 x i64], %1, [0 x i64], { i64, ptr }, [0 x i64] }
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%1 = type { [0 x i64], %2, [0 x i64], ptr, [0 x i64] }
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%2 = type { [0 x i64], %3, [0 x i64], %4, [0 x i8], i8, [7 x i8] }
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%3 = type { [0 x i64], { ptr, ptr }, [0 x i64], ptr, [0 x i8], i8, [7 x i8] }
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%4 = type { [0 x i64], { ptr, ptr }, [0 x i64], %5, [0 x i64] }
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%5 = type { [0 x i64], { ptr, ptr }, [0 x i64], ptr, [0 x i64] }
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%6 = type { [0 x i64], i64, [2 x i64] }
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%7 = type { [0 x i64], { ptr, ptr }, [0 x i64], %8, [0 x i64] }
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%8 = type { [0 x i64], ptr, [0 x i32], { i32, i32 }, [0 x i8], i8, [7 x i8] }
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%9 = type { [0 x i64], i64, [0 x i64], [0 x %10], [0 x i8], %11 }
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%10 = type { [0 x i8], i8, [31 x i8] }
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%11 = type {}
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%12 = type { [0 x i64], %13, [0 x i32], i32, [0 x i32], i32, [0 x i32] }
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%13 = type { [0 x i8], i8, [23 x i8] }
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%14 = type { [0 x i64], i64, [0 x i64], %15, [0 x i32], i32, [0 x i8], i8, [0 x i8], { i8, i8 }, [0 x i8], { i8, i8 }, [0 x i8], { i8, i8 }, [0 x i8], { i8, i8 }, [0 x i8], { i8, i8 }, [0 x i8], { i8, i8 }, [0 x i8], { i8, i8 }, [0 x i8], { i8, i8 }, [0 x i8], { i8, i8 }, [0 x i8], { i8, i8 }, [7 x i8] }
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%15 = type { [0 x i64], { ptr, i64 }, [0 x i64], i64, [0 x i64] }
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%16 = type { [0 x i64], %17, [0 x i64], %18, [0 x i64], %19, [0 x i64], i64, [0 x i8], { i8, i8 }, [6 x i8] }
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%17 = type { [0 x i32], i32, [27 x i32] }
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%18 = type { [0 x i64], i64, [6 x i64] }
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%19 = type { [0 x i8], i8, [103 x i8] }
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%20 = type { [0 x i64], ptr, [0 x i64], ptr, [0 x i64], ptr, [0 x i64] }
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%21 = type { [0 x i64], i64, [0 x i64], ptr, [0 x i64], [2 x i64], [0 x i64] }
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%22 = type { [0 x i8] }
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@var = external dso_local unnamed_addr constant <{ ptr, [8 x i8], ptr, [16 x i8] }>, align 8
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declare dso_local fastcc { ptr, ptr } @test2(ptr) unnamed_addr
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define void @test(ptr %arg, ptr %arg1, ptr %arg2) unnamed_addr personality ptr @personality {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0: # %bb
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -32(r1)
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; CHECK-NEXT: std r0, 48(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: li r4, 0
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; CHECK-NEXT: # %bb.1: # %bb9
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; CHECK-NEXT: bl test5
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; CHECK-NEXT: nop
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; CHECK-NEXT: rlwinm r4, r3, 8, 16, 23
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; CHECK-NEXT: # %bb.2: # %bb12
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; CHECK-NEXT: bl test3
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r1, r1, 32
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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bb:
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switch i64 undef, label %bb21 [
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i64 3, label %bb3
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]
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bb3: ; preds = %bb
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switch i3 undef, label %bb4 [
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i3 0, label %bb9
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i3 1, label %bb12
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]
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bb4: ; preds = %bb3
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unreachable
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bb5: ; No predecessors!
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br label %bb12
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bb6: ; No predecessors!
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br label %bb12
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bb7: ; No predecessors!
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br label %bb12
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bb8: ; No predecessors!
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br label %bb12
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bb9: ; preds = %bb3
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%tmp = call i8 @test5(ptr noalias nonnull readonly align 8 dereferenceable(64) undef), !range !0
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%tmp10 = zext i8 %tmp to i24
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%tmp11 = shl nuw nsw i24 %tmp10, 8
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br label %bb12
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bb12: ; preds = %bb9, %bb8, %bb7, %bb6, %bb5, %bb3
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%tmp13 = phi i24 [ 1024, %bb8 ], [ 768, %bb7 ], [ 512, %bb6 ], [ 256, %bb5 ], [ %tmp11, %bb9 ], [ 0, %bb3 ]
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%tmp14 = call fastcc align 8 dereferenceable(288) ptr @test3(ptr noalias nonnull readonly align 8 dereferenceable(24) undef, i24 %tmp13)
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br label %bb22
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bb15: ; No predecessors!
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%tmp16 = invoke fastcc { ptr, ptr } @test2(ptr nonnull align 8 dereferenceable(8) undef)
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to label %bb17 unwind label %bb18
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bb17: ; preds = %bb15
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invoke void @test4(ptr noalias readonly align 8 dereferenceable(40) @var)
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to label %bb23 unwind label %bb25
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bb18: ; preds = %bb15
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%tmp19 = landingpad { ptr, i32 }
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cleanup
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resume { ptr, i32 } undef
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bb20: ; No predecessors!
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invoke void @test4(ptr noalias readonly align 8 dereferenceable(40) @var)
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to label %bb24 unwind label %bb25
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bb21: ; preds = %bb
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unreachable
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bb22: ; preds = %bb12
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ret void
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bb23: ; preds = %bb17
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unreachable
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bb24: ; preds = %bb20
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unreachable
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bb25: ; preds = %bb20, %bb17
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%tmp26 = landingpad { ptr, i32 }
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cleanup
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resume { ptr, i32 } undef
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}
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declare dso_local fastcc ptr @test3(ptr, i24) unnamed_addr
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declare i32 @personality(i32, i32, i64, ptr, ptr) unnamed_addr
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declare void @test4(ptr) unnamed_addr
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declare i8 @test5(ptr) unnamed_addr
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!0 = !{i8 0, i8 5}
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