15e295d30a
The MI scheduler skips regions containing a single MI during scheduling. This can prevent targets that perform multi-stage scheduling and move MIs between regions during some stages to reason correctly about the entire IR, since some MIs will not be assigned to a region at the beginning. This makes the machine scheduler no longer skip single-MI regions. Only a few unit tests are affected (mainly those which check for the scheduler's debug output).
46 lines
1.5 KiB
LLVM
46 lines
1.5 KiB
LLVM
; REQUIRES: asserts
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; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -stop-after=postmisched -debug-only=machine-scheduler 2>&1 >/dev/null | FileCheck %s
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define void @pr47155() {
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; CHECK-LABEL: Machine code for function pr47155
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; CHECK: *** Final schedule for %bb.0 ***
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; CHECK: ********** MI Scheduling **********
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; CHECK-NEXT: pr47155:%bb.0 entry
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; CHECK: SU(0): INLINEASM &"mtlr 31"{{.*}}implicit-def early-clobber $lr
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; CHECK: Successors:
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; CHECK-NEXT: SU(1): Out Latency=0
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; CHECK-NEXT: SU(1): Ord Latency=0 Barrier
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; CHECK-NEXT: SU(1): INLINEASM &"mtlr 31"{{.*}}implicit-def early-clobber $lr8
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; CHECK: Predecessors:
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; CHECK-NEXT: SU(0): Out Latency=0
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; CHECK-NEXT: SU(0): Ord Latency=0 Barrier
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; CHECK-NEXT: ExitSU:
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entry:
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call void asm sideeffect "mtlr 31", "~{lr}"()
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call void asm sideeffect "mtlr 31", "~{lr8}"()
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ret void
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}
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define void @pr47156(ptr %fn) {
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; CHECK-LABEL: Machine code for function pr47156
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; CHECK: *** Final schedule for %bb.0 ***
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; CHECK: ********** MI Scheduling **********
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; CHECK-NEXT: pr47156:%bb.0 entry
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; CHECK: SU(0): INLINEASM &"mtctr 31"{{.*}}implicit-def early-clobber $ctr
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; CHECK: Successors:
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; CHECK-NEXT: SU(1): Out Latency=0
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; CHECK-NEXT: SU(1): MTCTR8 renamable $x3, implicit-def $ctr8
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; CHECK: Predecessors:
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; CHECK-NEXT: SU(0): Out Latency=0
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; CHECK-NEXT: Successors:
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; CHECK-NEXT: ExitSU:
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; CHECK-NEXT: SU(2):
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entry:
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call void asm sideeffect "mtctr 31", "~{ctr}"()
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tail call void %fn()
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ret void
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}
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